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FinFET ASICs for Networking, Data Center, AI and 5G

FinFET ASICs for Networking, Data Center, AI and 5G
by Daniel Nenni on 01-08-2018 at 12:00 pm

20947-samsung-ase-esilicon-rambus-nwl-hbm2-25d-serdes-webinar-semiwiki-400px.jpgOn the heels of successful seminars in Tokyo and Shanghai, eSilicon is starting the new year back in the cloud with a webinar version of the live events for those, like myself, who could not attend. The webinar will compress the 3 hour live event into 60 minutes which will provide a great place to start a conversation on your next chip for networking, data center, artificial intelligence, and 5G applications.

In talking to my paisan Mike Gianfagna, eSilicon presented a complete ecosystem to address the requirements of advanced ASICs for markets such as high-performance computing, networking, deep learning and 5G. Samsung Memory presented their HBM2 solutions, Samsung Foundry talked about their advanced 14nm FinFET solutions, ASE Group reviewed their advanced 2.5D packaging solutions, eSilicon presented ASIC and 2.5D design/implementation and IP solutions, Rambus detailed their high-performance SerDes solutions and Northwest Logic presented their HBM2 controller solutions.

Mike is one of the few people I work with that has more semiconductor experience than I do. In fact, I worked for Mike many many many years ago at Zycad and he is still one of my favorite bosses, which is saying something because I have worked for a LOT of people in the past 33 years.

The most common lunch conversation Mike and I have is “what’s next” for semiconductors, him on the ASIC side and me on the SemiWiki side. Based on his experience from the live seminars and my end of year wrap up on SemiWiki you will be seeing a lot more advanced ASICs for HPC, networking, AI, and the beginnings of 5G infrastructure. Not all of these chips will come from the top semiconductor companies of course, which brings us to the mighty ASIC business model that I have written about many times.

According to Mike, and I concur, many markets are initially enabled with semiconductor devices in the form of application-specific standard products (ASSPs) or field-programmable gate arrays (FPGAs). The recent rise of deep learning applications has created another ASSP-like option, the graphics processing unit (GPU). All of these technologies offer a predictable unit cost with a specific set of features. This usually works well until one of two things happens:

  • Volume and cost pressures grow to the point where buying a standard product where perhaps only 60 percent of the chip is used becomes a financial problem.
  • Competition in the market becomes so strong that differentiating with the same chip everyone else uses becomes a marketing problem.

    When one or both of the above situations occur, traditional and non-traditional chip companies turn to ASICs as a way to reduce unit cost (the chip does exactly what’s needed with no wasted silicon) or as a way to increase differentiation (you can optimize the chip for your application). The result being a more competitive chip, right?

    Mike makes a good point in regards to markets that are already high growth and highly competitive. Add to that the fact that the design cost of an ASIC is typically a very small part of the unit cost of the end system which makes ASICs a viable option if not a requirement, absolutely.

    Bottom line: Mike’s prediction and SemiWiki analytics preict a robust ASIC business for the HPC, networking, AI, and 5G infrastructure markets in 2018 which brings us to the upcoming webinar:

    FinFET ASICs for Networking, Data Center, AI and 5G Using 14nm 2.5D/HBM2 and SerDes
    The huge amount of data generated, moved, stored and analyzed around the world today has changed custom IC development forever. The massive, FinFET-class ASICs used in todayÂ’s networking, data center, artificial intelligence (AI) and 5G infrastructure applications require doing things in silicon that have never been done before.

    High-bandwidth memory (HBM2) addresses performance, power and size issues, but requires a 2.5D implementation. How do you find an ASIC ecosystem you can trust to build a 2.5D chip?

    We will present real case studies and roadmaps for high-performance FinFET ASICs. We will introduce a complete ecosystem with proven delivery of high-performance ASICs and 2.5D/HBM2 systems.

    Attendees will receive a new 2.5D/HBM2 white paper written by the HBM2 ecosystem, including presenting companies.

    Register for the 8:00-9:00 AM or 6:00-7:00 PM Pacific Time webinar.

    · Samsung: HBM2 memory solutions
    · Samsung: Foundry solutions including 14nm FinFET technology
    · ASE Group: advanced 2.5D packaging
    · eSilicon: ASIC and 2.5D design and implementation, HBM2 PHY, high-speed memories
    · Rambus: high-performance SerDes
    · Northwest Logic: HBM2 controller

    About eSilicon
    Silicon is an independent provider of complex FinFET-class ASIC design, custom IP and advanced 2.5D packaging solutions. Our ASIC+IP synergies include complete, silicon-proven 2.5D/HBM2 and TCAM platforms for FinFET technology at 14/16nm. Supported by patented knowledge base and optimization technology, eSilicon delivers a transparent, collaborative, flexible customer experience to serve the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets. www.esilicon.com