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3D Xpoint and the Future of Memory

3D Xpoint and the Future of Memory
by Scotten Jones on 09-15-2015 at 4:00 pm

Recently Intel and Micron announced a new three dimensional cross point (3D Xpoint) memory. The 3D Xpoint announcement has generated a lot of questions and interest in what this new memory is and where it may fit in the semiconductor market.

Existing solutions
Logic systems have a memory hierarchy with each tier optimized for a particular task. A typical hierarchy is:

  • Registers – on chip with the cores. Stores intermediate results during calculations, runs at the core speed, have small capacity (for speed) and wide data paths (for fast loading and unloading of data). Typically kilobytes of SRAM.
  • Cache – typically on-chip with the cores (used to be off-chip). Stores recently completed results and program instructions and data that are predicted to be needed by the core in the near future, bigger than the registers making access to data somewhat slower but still cache needs to be fast. Typically megabytes of SRAM.
  • Working memory – typically off-chip, often as multiple memory specific chips. Working memory stores programs that are currently running on the system and stores data currently being worked on by the system, is slower than cache and there is typically a lot more of it so it needs to be less expensive. Typically a few gigabytes of DRAM.
  • Long term storage – typically off chip in the form of a hard disc drive or in some portable systems as NAND Flash memory. Long term storage is where programs and data are stored even when a system isn’t running, much larger in capacity than the other types of memory outlined above storing more data and programs than could be loaded into main memory at one time, must be non-volatile, typically much slower and much less expensive than main memory. Typically many gigabytes to a terabyte of NAND Flash or a hard drive.

The memory type used for each tier in the hierarchy is determined by a set of tradeoffs in the memory characteristics.

SRAM is the fastest memory and has excellent endurance so it is used for registers and cache even though it is volatile (loses values when the power is turned off), takes up a lot of area and is relatively expensive. DRAM is slower than SRAM and volatile but it is cheaper than SRAM and has excellent endurance so it is used for main memory. NAND is non-volatile and less expensive than DRAM but it is slow and has poor endurance making it only suitable for long term storage.

Table 1 (source ITRS) compares the three types of memory discussed above

[TABLE] border=”1″
| style=”width: 133px” |
| style=”width: 126px” | DRAM
| style=”width: 138px” | NAND
| style=”width: 114px” | SRAM
| style=”width: 133px” | Cell type[SUP]a[/SUP]
| style=”width: 126px” | 1T1C
| style=”width: 138px” | 1T
| style=”width: 114px” | 6T
| style=”width: 133px” | Cell area[SUP]b[/SUP]
| style=”width: 126px” | 6F[SUP]2[/SUP], may go to 4F[SUP]2[/SUP]
| style=”width: 138px” | 4F[SUP]2[/SUP]
| style=”width: 114px” | 140F[SUP]2[/SUP]
| style=”width: 133px” | Access time (read/write/erase)
| style=”width: 126px” | <10/<10/<10ns
| style=”width: 138px” | 0.1/1.0/0.1ms
| style=”width: 114px” | 0.2/0.2/0.2ns
| style=”width: 133px” | Non-volatile[SUP]c[/SUP]
| style=”width: 126px” | No
| style=”width: 138px” | Yes
| style=”width: 114px” | No
| style=”width: 133px” | Endurance (cycles)
| style=”width: 126px” | Unlimited
| style=”width: 138px” | 1E6[SUP]d[/SUP]
| style=”width: 114px” | Unlimited

[SUP]a[/SUP]C is capacitor, T is transistor
[SUP]b[/SUP] F is feature size
[SUP]c[/SUP] Volatile lose data when power is removed, non-volatile retains data when power is removed
[SUP]d[/SUP] Some NAND Flash endurance may be as low as 1E4

Table 1. Comparison of DRAM, NAND and SRAM memory

Memory Evolution
All three forms of memory outlined above are facing scaling issues.

SRAM cell sizes continue to scale down as the technologies used to make processors move to smaller and smaller nodes, but the classic 6T SRAM cell is now often supplanted by 8T and 10T cells in the most critical paths.

The key issue in DRAM scaling is the capacitor. A minimum capacitance value is required in order to store values (electrons). In order to shrink the horizontal area of the capacitor very tall structures have been implemented and the dielectric has transitioned to high-k materials. The issue now is twofold, one is that capacitor heights are reaching practical limits, and two, achieving higher dielectric k values is becoming very difficult. There is a variety of high-k materials available with a range of k values, the fundamental problem is that as k values increase, the band gap of the material decreases increasing leakage. The solution to this has been the use of sandwich materials such the current ZAZ where a high band gap aluminum oxide is sandwiched between two layers of high-k zirconium oxide. The problem with a sandwich is the resulting k value is reduced by the aluminum oxide layer. There is a lot of work still being done on capacitor materials with aluminum doped titanium oxide looking promising but DRAM scaling likely only has one or two more nodes left. Current DRAM state-of-the-art is 20nm with possibly a 16nm and maybe a 12nm node in the future.

In NAND scaling the issue has been how to scale down while maintaining good control gate to floating gate coupling within a memory cell – without coupling to adjacent cells. Storing enough electrons is also an issue for further scaling and 2D NAND dimensions have gotten so small that very complex self-aligned quadruple patterning (SAQP) is required on several layers. In the NAND space 3D NAND has been introduced by Samsung as a 2D NAND successor. Samsung’s initial device stacked up 24 memory cell layers with a single bit per cell. Multiple producers are now introducing 48 layers devices with 3 bits per cell. 3D NAND is a new scaling paradigm where a 40nm technology is expected to be used with an increasing number of layers (eventually over 100) until a 1Tb NAND results. There is only one multi-patterning layer required in the device fabrication and the number of lithography layers stays essentially the same even as more memory layers and bits per device are produced. 3D NAND is so promising that Micron has announced 16nm will be their last 2D NAND generation and all their efforts going forward will be on 3D NAND.

3D Xpoint
At the introduction press conference Intel and Micron described their new 3D Xpoint memory as being 1,000 times faster than NAND Flash with 1,000 times the endurance. That is very impressive but still isn’t the speed or endurance required to replace DRAM. The density was described as 10 times as high as DRAM with a cost intermediate between DRAM and NAND.

The exact mechanism behind the 3D Xpoint wasn’t disclosed but each memory cell is a memory element that stores resistance values and a selector (1R1D). Existing memory cells store electrons placing a lower limit on how much the cell can scale, storing values as a resistance should remove those limitations. The memory cells are each located at the cross point between orthogonal bit and word lines. The initial device had two memory layers, further scaling of the device is possible in three ways:


  • Add more memory layers.
  • Scale dimensions in x and y.
  • Go from a single bit per cell to a multi-bit per cell.

    Our estimates for the die size suggest a 4F[SUP]2[/SUP] memory cell where F is approximately 25nm. Adding more memory layers should be straight forward but will require at least two mask layers for each memory layer and likely more. At a 25nm feature size the mask layers will be relatively complex and expensive multi-patterning layers. Scaling in x and y will require even more complex multi-patterning schemes at least until an alternative such as sufficiently high throughput EUV is available. Multi bit per cell was also mentioned as an option but how easy this is to implement isn’t clear.

    Our current calculations find that the bits per mm[SUP]2[/SUP]for the initial 3D Xpoint memory is lower than current state-of-the-art 2D or 3D NAND. We expect that with additional layers 3D Xpoint will exceed 2D NAND density but will lag behind 3D NAND. Furthermore, we believe 3D NAND has a cost scaling advantage over 3D Xpoint memory and will continue to be less expensive per bit.

    Micron is positioning 3D Xpoint as a Storage Class Memory that sits between main memory and long term storage. We believe this memory will find many interesting applications but will not directly replace DRAM due to speed and endurance issues and won’t replace NAND due to cost.

    This discussion of 3D Xpoint is an excerpt from a more detailed document we have produced for our Strategic Cost Model customers.

    What’s Next?
    3D Xpoint is an interesting memory technology and will likely stake out an applications space between DRAM and NAND, but there is still an issue with DRAM scaling. Micron Technologies’ road map lists a new memory A and new memory B. Memory A is the 3D Xpoint being introduced now with a second generation expected next year, but what is memory B expected in 2017?

    There has been a lot of talk for several years about MRAM being the successor to DRAM. MRAM stores memory values as magnetism, not electrons and so can theoretically scale down very small. MRAM also has the potential speed and endurance to be a direct replacement for DRAM. To-date MRAM has been nowhere near the density or cost required to replace DRAM but what if memory B is a multilayer cross point memory with MRAM cells at each cross point? The ability to stack multiple cells up as memory layers might finally get MRAM to a competitive density and ultimately cost to replace DRAM. This is only speculation on my part but a 3D DRAM replacement seems like a logical future direction.

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