As part of their webinar series, SemiWiki hosted one in June with the title “Five Reasons Why a High Performance Reconfigurable SmartNIC Demands a 2D NoC.” The talk by given by Scott Schweitzer, Sr. Manager, Product Planning at Achronix. Scott is a lifelong technology evangelist and focuses on recognizing technology trends and identifying ways to accelerate networking communications. I recently watched it on-demand.
Before I summarize Scott’s talk, let’s breakdown the long title of the webinar. First the NIC and the NoC. NIC stands for Network Interface Card and NoC here stands for “Network on a Chip.” This NoC is not to be confused with the other NOC which stands for Network Operations Center, both of course relating to communications. 2D NoC is analogous to a grid of highways that quickly gets traffic through to their final destinations. In the case of the NoC, it is data traffic. The pivotal part of the long title is “High Performance.”
To understand high-performance in this context, let’s look at an analogy that many of us can relate to. If a broadband connection into a home is very fast but the modem hardware slows things down, the benefit is lost. Similarly, if a home WiFi network is slow, the benefit of a very fast broadband connection is lost. But what if one already has a fast modem and a fast WiFi network? In reality, most home WiFi networks cannot fully benefit from the higher than 1Gbps broadband connections that are available to them. While this mismatch may not even be noticed at homes, today’s data centers, hyperscale data centers, edge AI applications, etc., cannot afford to tolerate these bottlenecks. This is the context for Scott’s talk.
Scott starts off by making a case for single-chip SmartNIC implementations at 100GbE and above. No contention there as on-chip communications are faster than when data paths having to jump through many different chips before getting to their final destinations. He states that studies show that a 2x10GbE interface network could move 25% more data than a 8xPCIeGen1 link can handle. That gap increases to 56% when we consider a 2x400GbE interface network with a 16xPCIeGen5 link. In other words, Ethernet bandwidths are fast outpacing PCIe speeds. Refer to Figure below. That shows the first of his five reasons for the need for high-performance SmartNICs overlayed on to a 2D NoC. The maximum data rate coming into a chip could be as high as 3.2Tbps if we consider a Cisco 5500 series router supplying the data. This external data has to be touched a number of times before sending to the host for processing.
Reasons 2 through 5:
The current generation of SmartNICs relies heavily on semiconductor devices with many processor cores to process packets. This approach, which is already challenged at 25GbE, becomes very difficult to scale beyond 100GbE.
Add virtualization requirements and software define (SD) overlay networks and we have increased the number of processing/touch points before the data can get to the final destination. The logical network (virtualization defined) may look like it has a couple of touch points. But the physical network through which the data is routed may have many SmartNICs through which the data has to go through. And each of these SmartNICs may have to do lot of work on the data before sending to the next SmartNIC.
More and more functions are being thrust upon the SmartNICs to handle. Security, filtering and key management are important functions that SmartNICs are tasked with. Processing data to identify if it is safe or not could be a simple task or a complicated deep analysis task depending on the application.
Offloading tasks that were traditionally handled by the host is becoming more common. For example, NVMe storage is being used like network attached storage with access managed by a SmartNIC.
The above reasons revolve around the need for having both reconfigurability and fast processing speed. A programmable-logic-based implementation is more efficient with packet processing than a processor-based implementation which requires executing multiple instructions for this processing. The same programmable-logic also enables the reconfigurability of the SmartNIC, which essentially boils down to solution flexibility.
It is a big benefit to be able to swap the algorithms running on these SmartNICs as the requirements of the supported applications evolve.
2D Network on Chip (NoC)
After handling more data and processing them very fast, it doesn’t make sense to wait. Like the phrase “hurry up and wait.” This is where overlaying the programmable-logic based SmartNIC on to a 2D NoC on the same FPGA platform comes in. As you see in the Figure below, the north-south and east-west data highways can get the data quickly to the host/final destination.
SmartNICs are being expected to handle more functionality and offer flexibility to handle changing requirements. They are expected to process incoming external data very efficiently and get the data to the final destination rapidly. Programmable-logic based single chip SmartNIC solution that leverages a 2D NoC offers an attractive approach as the gap between Ethernet bandwidths and PCIe speeds widen. You can watch the entire webinar on-demand by registering here.
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