In every semiconductor related field, innovation is the name of the game. Academic, non-profit and government research has been a consistent source of innovation. Look back at the US space program, basic science research and even military programs to see where much of the foundation of our current technological age came from. Indeed, you might not be sitting in front of your computer on the internet now, had it not been for ARPA’s work in developing internet hardware and protocols. Fortunately, there is a long tradition of leading technology companies helping facilitate advanced research.
Achronix, a company with a potentially game changing product for embeddable FPGA fabric, just announced a program to give access for their technology to academic and research entities. Their Research eFPGA Accelerator Program will allow researchers to use preconfigured Speedcore eFPGA IP for their research projects. While a commercial company would probably want a fully configurable and optimized Speedcore block, researchers can work with preconfigured blocks. This helps Achronix by lowering support costs and allowing the process run more quickly.
I recently spoke to Steve Mensor, VP of Marketing at Achronix, about this program to better understand what they want to accomplish. He said that because embeddable FPGA is new, there are lot of interesting problems that it can solve. He sees this program as a win-win. Achronix can learn from new usage scenarios that researchers devise, at the same time researchers benefit from being able to apply new technology. He is hoping that this program leads to many new ideas.
It’s also safe to say that once students and researchers learn how eFPGA and the tools used in the flow work, down the road they may find other new applications, either academic or potentially even commercial. Steve says that this will be a big benefit to users that have low volumes and could not afford the cost of developing new instances. Using preconfigured IP is cost effective for everyone involved, and there is no real penalty in area – due to the low volumes.
Achronix will supply fully qualified and characterized, silicon proven blocks on TSMC 16 FF+. They anticipate that AI/ML will be a big application area. eFPGA offers low latency, programmability and acceleration of parallel processing for AI/ML designs.
In addition to purely academic users, Achronix also has announced a program called the Test-Chip eFPGA Accelerator Program will help startups and small companies, and others, by making it easy to try out new architectures in silicon that use eFPGA fabrics. This program will let companies produce evaluation volumes of SOCs that use their eFPGA fabric. Just like the academic program, it will use pre-verified silicon blocks on TSMC 16 FF+.
Steve is betting that once institutions and companies try out eFPGA and their ACE tool set, they will see significant benefits. In the case of commercial users, this creates a lower cost and safe means to start building products with eFPGA. The Achronix website has full details on how to participate in both of these new programs.Share this post via:
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