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Webinar: Parasitic Debugging made easy!

Webinar: Parasitic Debugging made easy!
by Daniel Nenni on 12-03-2013 at 3:00 pm

We cordially invite you to attend this webinar and learn how to quickly debug post layout designs. Concept Engineering is a privately held company based in Freiburg, Germany. It was, founded in 1990 to develop and market innovative schematic generation and viewing technology for use with logic synthesis, verification, test automation and physical design tools. The company’s customers are primarily original equipment EDA tool manufacturers (OEMs), in-house CAD tool developers, semiconductor companies, IC/ASIC designers and FPGA designers.

Parasitic Debugging made easy!

[TABLE] cellspacing=”5″ style=”width: 540px”
|-
| colspan=”5″ style=”padding: 0px 20px; padding-top: 10px” | [TABLE] cellspacing=”5″
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| Date:
| December 11, 2013
|-
| Time:
| 10:00 am – 11:00 am (PST)
|-
| valign=”top” | Location:
| Online Webinar via WebEx
|-

REGISTER NOW

What you will learn:

• Render schematics on the fly for Spice level netlists to understand function of circuit easily. Supported dialects include SPICE, HSPICE, Spectre, Calibre, CDL, DSPF, SPEF, Eldo, PSPICE and IBIS

• Extract, navigate and save fragments of circuits as Spice netlists with the ‘cone view’, for reuse as IP or external use in partial simulation

• Drag & drop selected components/nets between all design views (schematic, logic cone, Parasitic window and source code view) to cross probe and shorten debug time, especially during tape-out for full chip debug

• Automatically create digital logic symbols and schematics from pure SPICE netlists for easy design exploration

• Visualize and analyze parasitic networks (Post layout formats: DSPF, RSPF, SPEF) and create SPICE netlists for critical path simulation

• Instantly turn off/on parasitic structures in SPICE circuits for better comprehension of CMOS function

• Export schematics and schematic fragments into Cadence Virtuoso Schematic for further optimization and debugging

• ERC Checking: Verify/debug connectivity especially for multi fan-in and fan-out nets by identifying floating input and output nets, heavy connected nets, etc.

• Generate design statistics & reports: Instance & primitive counts

• Extend functionality of SpiceVision to match project needs by interfacing with the open database through tcl scripts
|-

Concept Engineering’s products deliver the fastest, highest quality automatic schematic generation and viewing technology. They integrate easily into all EDA and CAD tools and design flows and run on Windows and Unix computing platforms.

  • Nlview™ Widgets – a family of GUI building blocks for design visualization (Tcl/Tk, MFC, Qt, Perl/TK and Java) that can be easily customized and seamlessly integrated into other EDA tools.
  • T-engine™ – an advanced visualization engine for transistor-level structures.
  • RTLvision® PRO – a graphical debugger for SystemVerilog, Verilog and VHDL based designs.
  • GateVision® PRO – a standalone design analyzer that generates easy-to-read schematics from any Verilog or EDIF netlist. GateVision is a point tool that fits into most design flows.
  • SpiceVision® PRO – an interactive visualization tool that can be used to debug and analyze SPICE circuits and SPICE models.
  • SGvision™ PRO – a customizable mixed-mode debugger (SPICE and Verilog).
  • StarVision™ PRO – a customizable mixed-signal and RTL debugger (SPICE, VHDL, Verilog and SystemVerilog).

REGISTER NOW

lang: en_US


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