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Webinar 800x100 (1) 
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Synopsys
Posted on

Double Patterning Verification

Double Patterning Verification
by Paul McLellan on 12-10-2012 at 3:03 am
Categories: EDA, Synopsys

You can’t have failed to notice that 20nm is coming. There are a huge number of things that are different about 20nm from 28nm, but far and away the biggest is the need for double patterning. You probably know what this is by now, but just in case, here is a quick summary.

Lithography is done using 193nm light. Today we use immersion… Read More

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Second FPGA to the right, and straight on ‘til it works

Second FPGA to the right, and straight on ‘til it works
by Don Dingee on 11-26-2012 at 6:00 pm
Categories: EDA, FPGA, Synopsys

In a fantasy world where there were no coding errors or integration issues, FPGA designs would fly straight through synthesis easily and quickly. Maybe that world does exist somewhere. For the rest of us, who have experienced the agony of running a large FPGA design – again – only to find another error and have to start over, there … Read More

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How much SRAM proportion could be integrated in SoC at 20 nm and below?

How much SRAM proportion could be integrated in SoC at 20 nm and below?
by Eric Esteve on 11-20-2012 at 4:45 am
Categories: IP, Synopsys

Once upon a time, ASIC designers were integrating memories in their design (using a memory compiler being part of the design tools provided by the ASIC vendor), then they had to make the memory observable, controllable… and start developing the test program for the function, not a very enthusiastic task (“AAAA” and “5555” and other… Read More

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Next Generation FPGA Prototyping

Next Generation FPGA Prototyping
by Paul McLellan on 11-12-2012 at 7:00 am
Categories: EDA, FPGA, Synopsys

One technology that has quietly gone mainstream in semiconductor design is FPGA prototyping. That is, using an FPGA version of the design to run extensive verification. There are two approaches to doing this. The first way is simply to build an prototype board, buy some FPGAs from Xilinx or Altera and do everything yourself. The… Read More

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Static Timing Analysis for Memory Characterization

Static Timing Analysis for Memory Characterization
by Daniel Payne on 11-11-2012 at 6:18 pm
Categories: EDA, Synopsys

Modern SoC (System On Chip) designs contain a larger number of RAM (Random Access Memory) instances, so how do you know what the speed, timing and power are for any instance? There are a couple of approaches:
[LIST=1]

  • Trust the IP supplier to give you models that use polynomial equations to curve-fit the performance numbers based
    • … Read More
    Posted on

    Simulation: Expert Insights into Modeling Microcontrollers @ Renesas DevCon

    Simulation: Expert Insights into Modeling Microcontrollers @ Renesas DevCon
    by Holly Stump on 10-25-2012 at 9:03 pm
    Categories: EDA, Events, Synopsys

    “Simulation: Expert Insights into Modeling Microcontrollers” was the recent panel hot topic at Renesas DevCon2012, featuring Paolo Giustoof GM, Mark Ramseyerof Renesas, Marc Serughettiof Synopsys, Jay Yantchevof ASTC / VWorks, and Simon Davidmannof Imperas.
    … Read More

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    Learning about MEMS in Israel from: EDA companies, Foundry, University, Users

    Learning about MEMS in Israel from: EDA companies, Foundry, University, Users
    by Daniel Payne on 10-23-2012 at 12:24 pm
    Categories: EDA, Synopsys

    In April I attended and blogged about a webinar on MEMS and IC co-design hosted by two EDA companies: SoftMEMS and Tanner EDA. On October 30th you can attend a full-day event in Israel that is more comprehensive than the webinar that I attended.… Read More

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    TSMC dilemma: Cadence, Mentor or Synopsys?

    TSMC dilemma: Cadence, Mentor or Synopsys?
    by Eric Esteve on 10-18-2012 at 4:49 am
    Categories: Cadence, EDA, Foundries, Siemens EDA, Synopsys, TSMC

    Looking at the Press Release (PR) flow, it was interesting to see how TSMC has solved a communication dilemma. At first, let’s precise that #1 Silicon foundry has to work with each of the big three EDA companies. As a foundry, you don’t want to lose any customer, and then you support every major design flow. Choosing another strategy… Read More

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    IP-SoC 2012 Conference: don’t miss keynotes talk from Cadence, Synopsys, STMicroelectronics…

    IP-SoC 2012 Conference: don’t miss keynotes talk from Cadence, Synopsys, STMicroelectronics…
    by Eric Esteve on 10-17-2012 at 4:47 am
    Categories: Cadence, EDA, Events, Synopsys

    … Mentor Graphics, Design & Reuse or Gartner. The IP-SoC conference in Grenoble has been the very first 100% dedicated to Design IP, created by Gabriele Saucier 20 years ago, when “reuse” was more a concept than a reality within the design teams, and when Design IP was far to be a sustainable business.

    Pr Gabriele Saucier had the… Read More

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    Altera’s Use of Virtual Platforms

    Altera’s Use of Virtual Platforms
    by Paul McLellan on 10-11-2012 at 9:00 pm
    Categories: EDA, FPGA, Synopsys

    Altera have been making use of Synopsys’s virtual platform technology to accelerate the time to volume by letting software development proceed in parallel with semiconductor development so that the software development does not need to wait until availability of hardware.

    In the past, creating the virtual platform … Read More