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IP-SoC 2012 Conference: don’t miss keynotes talk from Cadence, Synopsys, STMicroelectronics…

IP-SoC 2012 Conference: don’t miss keynotes talk from Cadence, Synopsys, STMicroelectronics…
by Eric Esteve on 10-17-2012 at 4:47 am

… Mentor Graphics, Design & Reuse or Gartner. The IP-SoC conference in Grenoble has been the very first 100% dedicated to Design IP, created by Gabriele Saucier 20 years ago, when “reuse” was more a concept than a reality within the design teams, and when Design IP was far to be a sustainable business.

Pr Gabriele Saucier had the intuition that this concept would turn into a real business, and created “Design & Reuse”, the well-known IP portal, some years after the conference had started. Now, in 2012, Design IP and Computer Aided Engineering (CAE), both market segment as defined by EDAC, are weighting almost the same:

EDAC report revenues of $2,292 million for CAE in 2011 and $1,580 million for Design IP.

But, if you look at Design IP results as reported by Gartner, Design IP segment reach $1,910 million. And my guess is that some Design IP sales are not accounted by EDAC or Gartner, like these sold directly by the Silicon Foundries, by certain ASIC design houses like Global Unichip or Open Silicon, or even that some IP are directly traded between chip makers. Thus, estimating the IP market to be a two billion plus ($2.2B ?) looks realistic.

IP and EDA are both essential building blocks for the semiconductor industry. It was not clear back at the end of the 90’s that IP will become essential: at that time, the IP concept was devalued by some products exhibiting poor quality level, un-efficient technical support, leading program manager to be very cautious to simply decide to buy. Making was sometimes more efficient… In the meantime, the market has been cleaned up, the poor quality product suppliers disappearing (being bankrupt or sold for asset) and the remaining IP vendors have understood the lesson.

Today, none of the vendor launching a protocol based (digital) function would take the chance to launch a product which has not passed an extensive verification program, and mixed-signal IP vendors know that only Silicon proven functions will really sale. This leaves very small room for low quality products, the IP market is now mature and consolidating, even if some new comers are doing pretty well, especially in the PHY (Cosmic Circuits, VSemiconductor…), Chip Infrastructure (Arteris going from $5M in 2010 to $15M in 2011) and some promising companies, like Imagination Technologies or CEVA, finally make it, thanks to the smartphone explosion!

IP-SoC conference last two days, December 4 and 5, so the program is wide, here is an extract:

Keynote Talks
IP Business: Status and Perspectives by Gabriele Saucier, CEO, Design And Reuse

Semiconductor IP market overview” by Ganesh Ramamoorthy, Research Director, Gartner Inc

Managing the IP Sourcing Process: an IDM Perspective” by Philippe Quinio, Group Vice President of IP Sourcing & Strategy, STMicroelectronics

Cloud and Mobility: Disrupting the IP Ecosystem” by Martin Lund, Senior Vice President, Research and Development, SoC Realization Group, Cadence

Keynote Talk” by Joachim Kunkel, Senior Vice President and General Manager, Solutions Group, Synopsys

Power is now a Software Issue” by Colin Walls, Mentor Graphics

Invited Talks

Duopoly, Monopoly à Opportunity” by Marc Miller, Sr. Director of Marketing, Tabula

µfluidic applications: an upcoming Eldorado for µelectronic ?” by CEA

If you want to register, just go to Design & Reuse web site, here

If you come, we should meet, as I plan to attend to the conference, and present a paper. The topic? I will let you know in a next blog. The presentation will certainly be IP centric, and you most probably will hear about Mobile Express, PHY IP, MIPI… just stay tuned.

Eric Esteve


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