Synopsys just announced the availability of their IP solution supporting CXL (Compute Express Link). This new protocol is going to be an important component for several applications expected to be shipping starting in 2021. CXL is an alternate protocol that runs on the same physical layer as PCI Express (PCIe). Among other usages, PCIe is the protocol running over the expansion slots on all PCs. Other standards have been written on top of the PCIe electrical interface including the laptop expansion card interface ‘ExpressCard’ and the serial computer storage interface SATA Express. In data centers, many applications have become based on special hardware plugged into PCs via the PCIe slots on the motherboards. Those specialized applications to some extent have been held back by the limitations in the PCIe protocol. CXL is the new standard to address the needs of these new applications while maintaining backward compatibility with PCIe.
We have all heard of the explosion in machine learning and artificial intelligence. These solutions are predominantly based on either GPU or FPGA accelerators. There will soon be an onslaught of cards with application-specific processors from any number of different processor architectures to support applications such as image, facial, encryption/decryption, various video processing functions, storage class memory, voice recognition, big data analytics, and other capabilities that all depend on a fast host connection while running in the PCIe slots. With so much intelligence available in the expansion cards, more was needed from the interface protocol – specifically the sharing of cache and memory data between the host processor and the accelerator card’s processors. CXL addresses this for several type of systems by supporting low latency and cache coherency.
The most significant feature of CXL is that it uses three unique protocols – CXL.io which is used for configuration and data management, CXL.cache which enables an attached device to cache data from the host’s memory, and CXL.mem which allows a host processor to access attached memory in a CXL device using standardized transactions. These protocols allow the attached accelerators to work more cleverly and efficiently with the host processor, and potentially through the host processor cache, with other attached accelerators. Keep in mind that PCIe is a point-to-point connection model, not a bus model. Each of the attached devices has a dedicated channel to the host. The host processor manages coherency of data cached by the attached devices.
So why do I think that this will be important in 2021? Easy, future Intel CPUs will support PCIe 5.0 and CXL, beginning in 2021. In March, we heard that “Intel sees CXL as being an alternate protocol running over the PCIe physical layer. At first, CXL will use 32Gbps PCIe Gen5 pipes, but Intel and the consortium plan to aggressively drive towards PCIe Gen6 (and theoretically beyond) to scale.” In July, AMD also signed on to CXL. While AMD is also in other potentially competing consortiums, Intel is only backing CXL for the protocol in this part of the computing architecture. There are also many other prominent companies backing this standard. By market strength alone, I would expect it to win, but beyond that, it seems like a very efficient approach as well.
Synopsys has announced a quite complete CXL solution. The DesignWare® Compute Express Link (CXL) IP solution consists of a controller, PHY, and verification IP. Synopsys’ CXL IP solution is compliant with the CXL 1.1 specification and supports all three CXL protocols (CXL.io, CXL.cache, CXL.mem) and device types to meet specific application requirements. And, of course, CXL IP is built on Synopsys’ DesignWare IP for PCI Express 5.0. Most importantly, you can license and start designing with this solution now for products shipping in 2021, when we expect Intel to be shipping systems supporting CXL as well.