Tag: CXL

Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library

Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library
by Admin on 04-09-2025 at 2:36 am

As hyperscaler chiplet and SoCs grow in complexity, integrating and validating multiple high-speed and low-speed interface protocols—such as PCIe, CXL, UCIe, AMBA, AXI, AHB, CHI, CSI2, and DSI2, can be a significant challenge. Design Verification Engineers and Technical Managers must ensure seamless protocol compliance

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Scaling AI Data Centers: The Role of Chiplets and Connectivity

Scaling AI Data Centers: The Role of Chiplets and Connectivity
by Kalar Rajendiran on 11-26-2024 at 6:00 am
Categories: AI, Alphawave Semi, Chiplet, IP, Silicon Photonics

Building the Modern Data Centre AI Compute Nodes

Artificial intelligence (AI) has revolutionized data center infrastructure, requiring a reimagining of computational, memory, and connectivity technologies. Meeting the increasing demand for high performance and efficiency in AI workloads has led to the emergence of innovative solutions, including chiplets, advanced… Read More

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Samtec Paves the Way to Scalable Architectures at the AI Hardware & Edge AI Summit

Samtec Paves the Way to Scalable Architectures at the AI Hardware & Edge AI Summit
by Mike Gianfagna on 11-14-2024 at 6:00 am
Categories: AI, Events, Samtec, Semiconductor Services

Samtec Paves the Way to Scalable Architectures at the AI Hardware & Edge AI Summit

AI is exploding everywhere. We’ve all seen the evidence. The same thing is happening with AI conferences. The conference I will discuss here began in 2018 as the AI Hardware Summit. The initial venue was the Computer History Museum in Mountain View, CA. Like most things AI, this conference has grown substantially in a relatively… Read More

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Synopsys Powers World’s Fastest UCIe-Based Multi-Die Designs with New IP Operating at 40 Gbps

Synopsys Powers World’s Fastest UCIe-Based Multi-Die Designs with New IP Operating at 40 Gbps
by Kalar Rajendiran on 09-23-2024 at 10:00 am
Categories: 3D IC, AI, Automotive, Chiplet, EDA, IP, Synopsys

Synopsys 40G UCIe IP Solution

As the demand for higher performance computing solutions grows, so does the need for faster, more efficient data communication between components in complex multi-die system-on-chip (SoC) designs. In response to these needs, Synopsys has introduced the world’s fastest UCIe-based IP solution, capable of operating at a groundbreaking… Read More

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The Impact of UCIe on Chiplet Design: Lowering Barriers and Driving Innovation

The Impact of UCIe on Chiplet Design: Lowering Barriers and Driving Innovation
by Kalar Rajendiran on 08-15-2024 at 6:00 am
Categories: AI, Cadence, Chiplet, EDA, IP

Comparative Analysis of Chiplet Interconnect Standards (Physical Layer)

The semiconductor industry is experiencing a significant transformation with the advent of chiplet design, a modular approach that breaks down complex chips into smaller, functional blocks called chiplets. A chiplet-based design approach offers numerous advantages, such as improved performance, reduced development … Read More

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Alphawave Semi Tapes Out Industry-First, Multi-Protocol I/O Connectivity Chiplet for HPC and AI Infrastructure

Alphawave Semi Tapes Out Industry-First, Multi-Protocol I/O Connectivity Chiplet for HPC and AI Infrastructure
by Kalar Rajendiran on 07-29-2024 at 6:00 am
Categories: AI, Alphawave Semi, Chiplet, IP

Industry First, Multi Protocol IO Connectivity Chiplet

In the rapidly evolving landscape of high-performance computing (HPC) and artificial intelligence (AI), the demand for increased processing power, efficiency, and scalability is ever-growing. Traditional monolithic chip designs are increasingly unable to keep pace with these demands, leading to the emergence of chiplets… Read More

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AI Booming is Fueling Interface IP 17% YoY Growth

AI Booming is Fueling Interface IP 17% YoY Growth
by Eric Esteve on 07-11-2024 at 6:00 am
Categories: IP, IPnest, Semiconductor Services
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IF 2018 2027no$

AI explosion is clearly driving semi-industry since 2020. AI processing, based on GPU, need to be as powerful as possible, but a system will reach optimum only if it can rely on top interconnects. The various sub-system parts (memory, processor, co-processor, network) need to be connected with interface links with ever more bandwidth… Read More

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Driving Data Frontiers: High-Performance PCIe® and CXL® in Modern Infrastructures

Driving Data Frontiers: High-Performance PCIe® and CXL® in Modern Infrastructures
by Kalar Rajendiran on 06-10-2024 at 10:00 am
Categories: AI, Alphawave Semi, IP

Alphawave Ecosystem Collaborative Partners

The increasing demands of data-intensive applications necessitate more efficient storage and memory utilization. The rapid evolution of AI workloads, particularly with Generative AI (GenAI), demands infrastructure that can adapt to diverse computational needs. AI models vary widely in resource requirements, necessitating… Read More

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AI System Connectivity for UCIe and Chiplet Interfaces Demand Escalating Bandwidth Needs

AI System Connectivity for UCIe and Chiplet Interfaces Demand Escalating Bandwidth Needs
by Kalar Rajendiran on 05-27-2024 at 10:00 am
Categories: 3D IC, AI, Alphawave Semi, IP

Alphwave Semi UCIe PHY Support for All Package Types

Artificial Intelligence (AI) continues to revolutionize industries, from healthcare and finance to automotive and manufacturing. AI applications, such as machine learning, deep learning, and neural networks, rely on vast amounts of data for training, inference, and decision-making processes. As AI algorithms become … Read More

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Webinar: Samtec and Achronix Expand AI in the Data Center

Webinar: Samtec and Achronix Expand AI in the Data Center
by Mike Gianfagna on 05-09-2024 at 10:00 am
Categories: Achronix, AI, Events, Samtec

Webinar Samtec and Achronix Expand AI in the Data Center

The performance demands of data centers continue to grow, driven to large degree by the ubiquitous use of complex AI algorithms. On April 25, Embedded Computing Design held an informative webinar on this topic. Two experts looked at the problem from the standpoint of processor architecture and communication strategies, which… Read More