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WIKI Multi FPGA Design Partitioning 800x100 
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Aldec
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Aldec increasing the return on simulation

Aldec increasing the return on simulation
by Don Dingee on 01-19-2015 at 10:00 pm
Categories: Aldec, EDA

Debate rages about which approach is better for SoC design: simulation, or emulation. Simulation proponents point to software saving the need for expensive hardware platforms. Emulation supporters stake their claims on accuracy and the incorporation of real-time I/O. A few years back, some creative types coined the term SEmulation,… Read More

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Verilog-AMS connects T-SPICE and Riviera-PRO

Verilog-AMS connects T-SPICE and Riviera-PRO
by Don Dingee on 12-20-2014 at 7:00 am
Categories: Aldec, EDA

With advances in available IP, mixed signal design has become much easier. Mixed signal verification on the other hand is becoming more complicated. More complexity means more simulation, and in the analog domain, SPICE-based techniques grinding away on transistor models take a lot of precious time. Event-driven methods like… Read More

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Verification plans overcome hope-based coverage

Verification plans overcome hope-based coverage
by Don Dingee on 11-29-2014 at 7:00 am
Categories: Aldec, EDA

Coverage is an important yet elusive metric for design verification. It often seems 90% of coverage comes with 10% of the effort, and getting the final 10% covered takes the remaining 90% of a project. Usually, it takes another tool or methodology to get at the 10% the first tool missed. With 100% closure difficult, most teams inspect… Read More

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3 reasons to focus on hardware dependent software

3 reasons to focus on hardware dependent software
by Don Dingee on 10-25-2014 at 4:00 pm
Categories: Aldec, EDA

Why is software for modern SoCs so blasted expensive to develop? One reason is more software is being developed at the kernel layer – hardware dependent software, or HdS. Application software often assumes the underlying hardware, operating system, communication stacks, and device drivers are stable. For HdS, this flawed assumption… Read More

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Dominating FPGA clock domains and CDCs

Dominating FPGA clock domains and CDCs
by Don Dingee on 09-26-2014 at 7:00 am
Categories: Aldec, EDA, FPGA

Multiple clock domains in FPGAs have simplified some aspects of designs, allowing effective partitioning of logic. As FPGA architectures get more flexible in how clock domains, regions, or networks are available, the probability of signals crossing clock domains has gone way up.… Read More

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Another debug view in the UVM Toolbox

Another debug view in the UVM Toolbox
by Don Dingee on 08-17-2014 at 1:00 am
Categories: Aldec, EDA

One of the biggest endearing qualities of a debug environment for any type of coding is availability of multiple ways to accomplish a task. Whether the preference is keyboard shortcuts, mouse left-click drill-down and right-click pull-down menus, source code view, hierarchical class view, or graphical relationship view, … Read More

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Then, Python walked in for verification

Then, Python walked in for verification
by Don Dingee on 07-31-2014 at 12:00 am
Categories: Aldec, EDA, FPGA

Go ahead – type “open source” into the SemiWiki search box. Lots of recent articles on the IoT, not so many on EDA tools. Change takes a while. It has only been about five years since the Big Three plus Aldec sat down at the same table to work on UVM. Since then, Aldec has also gotten behind OS-VVM, and is now linked to a relatively new open… Read More

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Real FPGAs don’t eat fake test vectors

Real FPGAs don’t eat fake test vectors
by Don Dingee on 06-26-2014 at 8:00 am
Categories: Aldec, EDA, FPGA

Vector blasting hardware is as old as digital test methodology itself. In the days of relatively simple combinational and finite state machine logic, a set of vectors aimed broadside at inputs could shake loose most faults with observable outputs. With FPGAs, creating an effective set of artificial test vectors has become a lot… Read More

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Aldec Can Ensure Smooth System Integration

Aldec Can Ensure Smooth System Integration
by Luke Miller on 06-17-2014 at 9:00 pm
Categories: Aldec, EDA

Tools, tools, tools. Designs are rapidly changing, JESD204b, Hybrid Memory cube and all other Gigabit serialization schemes are here to stay. RIP DDR. This means board level simulations with respect to firmware (FPGA) are going to be more challenging than ever. Why? you ask, especially if the board layout is simpler? True, but… Read More

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Aldec is Celebrating 30 Years @ #51DAC!

Aldec is Celebrating 30 Years @ #51DAC!
by Daniel Nenni on 05-02-2014 at 8:00 am
Categories: Aldec, EDA

Dr. Stanley Hyduke founded Aldec in 1984 and their first product was delivered in 1985, named SUSIE (Standard Universal Simulator for Improved Engineering), a gate-level, DOS-based simulator. The SUSIE simulator was priced lower than other EDA vendor tools from the big three: Daisy, Mentor and Valid (aka DMV). Today, Aldec … Read More