Taming Concurrency: A New Era of Debugging Multithreaded CodeAs modern computing systems evolve toward greater parallelism,…Read More
Perforce Webinar: Can You Trust GenAI for Your Next Chip Design?GenAI is certainly changing the world. Every day…Read More
A Principled AI Path to Spec-Driven VerificationI have seen a flood of verification announcements…Read More
448G: Ready or not, here it comes!The march toward higher-speed networking continues to be…Read More
Should the US Government Invest in Intel?“Most companies don’t die because they are wrong;…Read More
Veriest recently hosted a webinar focusing on RISC-V as a forerunner of ongoing open-source revolution in chip design. Speakers were distinguished professionals from industry and academia. Webinar covered topics from market trends to open-source hardware initiatives, tools and methodologies.
Zvonimir Bandić: RISC-V … Read More
Dan is joined by Balaji Baktha, founder and CEO of Ventana Micro. Balaji explores the application of RISC-V in high-performance applications and the specific advantages of a chiplet-based approach.
RISC-V Summit Panel: https://www.youtube.com/watch?v=duZaAhWxhWM
The views, thoughts, and opinions expressed in these… Read More
I’ve been noticing over the last few years that electronic design automation (EDA) vendors just love to talk about artificial intelligence (AI) and machine learning (ML), sometimes with deep learning (DL) and neural networks tossed in as well. It can get a bit confusing since these terms are used in two distinct contexts. The first… Read More
Combining simulation and symbolic methods is an attractive way to excite rare branches in block-level verification, but is this method really scalable? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO) and I continue our series on research ideas. As always,… Read More
In 2014, many of the customers that my team and I supported in North America were still using HFSS 3D to model boards and packages. These customers were content with that interface, able to get their models setup quickly, and were okay with the solution times because when HFSS gave them an answer, they knew it was the right answer. I … Read More
The incredible growth that the semiconductor industry has enjoyed over the last several decades is attributed to Moore’s Law. While no one argues that point, there is also industry wide acknowledgment that Moore’s Law started slowing down around the 7nm process node. While die-size reductions still scale, performance jumps… Read More
My third event at DAC on Monday was all about using EDA tools in the Cloud, and so I listened to Craig Johnson, VP EDA Cloud Solutions, Siemens EDA. Early in the day I heard from Joe Sawicki, Siemens EDA, on the topic of Digitalization.
Why even use the Cloud for EDA? That’s a fair question to ask, and Craig had several high-level… Read More
Paul, Raúl and I are having fun with our Innovation in Verification series, and you seem to be also, judging by the hit rates we’re getting. We track these carefully to judge what you find most interesting and what seems to fall more under the category of “Meh”. Paul and others also get informal feedback in client meetings but it would… Read More
Now that the 58th Design Automation Conference held this year in San Francisco has concluded, we take a minute to look back at the results and ascertain what it meant for our company.
Unfortunately, many popular tradeshows held in the time of Covid have suffered a drop in attendance, and DAC was no exception. Despite this however,… Read More
PCIe is a prevalent and popular interface standard that is used in just about every digital electronic system. It is used widely in SOCs and in devices that connect to them. Since it was first released in 2003, it has evolved to keep up with rapidly accelerating needs for high speed data transfers. Each version has doubled in throughput,… Read More
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Should the US Government Invest in Intel?