SEMICON West’s “Bridging design and Manufacturing with AI” Design Session Explores AI as Practical Lever Across Entire Lifecycle

By Julie Rogers, Executive Director, Electronic System Design Alliance

2026 is “Bridging Design and Manufacturing with AI” during a day-long session Tuesday, October 13, from 10:30 a.m. to 4:30 p.m. at San Francisco’s Moscone Center, North Hall, Lower Level, Room 20.

The Design Session hosted and organized by the Electronic System Design Alliance (ESDA) is set to explore how AI serves as a practical lever across the entire lifecycle, from architecture exploration and verification to intelligent DFM, virtual metrology, predictive maintenance, and more.

I invite you to join us to learn where AI is delivering measurable impact, what data and infrastructures are required, and how design houses, foundries, systems companies, and equipment makers can collaborate to accelerate semiconductor innovation.

Our varied program starts with a visionary keynote presentation from Dr. L.C. Lu, Senior Fellow and Vice President, Research & Development/Design and Technology Platform at TSMC. He will describe “Scaling Leadership Silicon with AI.”

Immediately following is Jean-Philippe Fricker, Co-Founder and Chief System Architect from Cerebras. He will offer a look at Cerebras’ system-level decisions behind its CS-4 system and the Cerebras Nexus architecture with “Building Next-Gen AI: Redesigning Wafer-Scale Computing for Hyperscale.”

Subi Kengeri, Corporate Vice President and GM, Systems to Materials (STM) at Applied Materials, is our next presenter and will discuss “AI Enabled System Technology Co-Optimization (STCO) for Advanced Nodes.”

Lunch, provided by SEMI, follows with an IEEE-hosted panel “The True Value and Cost of Agentic AI in SoC Design and Manufacturing” moderated by Wally Rhines, CEO of Silvaco and featuring five senior-level semiconductor executives: Subi Kengeri, Applied Materials; Arif Khan, Vice President, Product Management at Marketing, Silicon Solutions Group, Cadence; Dr. David M. Fried, Chief AI Officer and Corporate Vice President, Semiverse Solutions, Lam Research; Dr. Vikas Sharma, Sr. Director, Sr. Principal Engineer, AI Applied Research Group, Intel Foundry; and Aman Joshi, Vice President, Design, Enablement and Alliances (IP, EDA, AI, Cloud), Sandisk.

After the panel, Lam Research’s Fried will present “From Process to Chips: How Can AI Increase Velocity in Chip Manufacturing?” that proposes analyzing the holistic picture of SoC design and manufacturing in the context of Agentic AI.

As the session moves on, Dr. Kimon W. Michaels, Executive Vice President of Products and Solutions, PDF Solutions, will present “From Front-End to Advanced Packaging: Scalable AI-Ready Data Platform, Secure Data Exchange and Ecosystem Collaboration.”

Silvaco’s Rhines will present on “Agentic AI Driven Manufacturing,” while Intel’s Sharma will report on “AI in Technology Development.” Cadence’s Khan will address “IP In AI Based Silicon Design” followed by the concluding presentation by Madhulima Tewari, CEO of VerifAIX.

Earlier in the day, Ed Sperling, Editor-in-Chief of Semiconductor Engineering, sits down with Sassine Ghazi, President and CEO of Synopsys for a Fireside Chat as part of the CEO Summit Keynote program. The chat will take place at the Moscone Center, North Hall, Lower Level, CEO Summit Stage starting at 9:20 a.m.

Special thanks to Dr. Ming Zhang, Vice President at PDF Solutions, who serves as event Chair and morning moderator. “Semiconductor design is shifting toward bespoke devices driven by domain-specific AI, chiplets, and application-tailored architectures, raising the bar for design agility, verification speed, and rapid iteration,” said Zhang. “This shift demands more flexible manufacturing: faster new product introduction, tighter bidirectional feedback between design and manufacturing, and resilient supply strategies. The emerging trends that will be discussed during the SEMICON West Design Session are relevant to all members of the semiconductor industry, making it a must-attend event.”

Thanks also go to Yatin Trivedi, Head of Semiconductor Center of Excellence (CoE) at Capgemini Engineering, our afternoon moderator and organizer of the lunch panel. “We took special care with the afternoon session to present realistic scenarios related to implementing AI-driven design and manufacturing processes to compress time to silicon and practical panel on the cost of implementing AI,” he noted. “All are meant to be timely and thought provoking.”

Learn more about the ESDA Design Session.

Registration is open. Register today and join us to learn where AI is delivering measurable impact for design and manufacturing.

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