Latest Savage on Security Webinar Focuses on Gen-AI for Chip Design and Security

Key Takeaways from the webinar:

Multi-agent intelligent assistant systems of the future will be architected to automate and augment SoC design and security verification and redefining semiconductor innovation, reshaping design, verification and security for the next generation of trusted silicon.

The ESD Alliance is delighted to welcome back Warren Savage host of the next Savage on Security Webinar “Gen-AI for Chip Design & Security” a look at how multi-agent intelligent assistant systems of the future will be architected to automate and augment SoC design and security verification. It will be held Thursday, September 10, at 9am PDT and Semi Wiki readers are invited to participate.

Warren, whom many of you remember as the Founder of IPextreme (now Silvaco), is a Researcher at the University of Maryland Applied Research Laboratory for Intelligence and Security and our go-to for all things chip security. He and his webinar guest Mark M. Tehranipoor from the University of Florida’s Department of Electrical and Computer Engineering will examine how multi-agent AI is redefining semiconductor innovation, reshaping design, verification and security for the next generation of trusted silicon.

According to Warren, he and Mark will look at the framework for multi-agent intelligent assistant systems that integrates design synthesis, threat modeling, formal reasoning, runtime monitoring strategies and hardware–software co-verification into a cohesive workflow. Systems like this point to a future of self-optimizing, security-aware and continuously verified silicon where AI-driven design environments will be able to accelerate innovation and fundamentally redefine how engineers conceive, build and trust next-generation microelectronic systems.

Registration is open. Pricing for SEMI members is $25. Non-member pricing is $50.

Students should contact Paul Cohen (pcohen@semi.org) for pricing.

Need more coaxing before joining us to learn what happens when AI takes on the hardest parts of chip design and security? Read the longer description below.

Designing functionally correct, high-performance, and provably secure SoCs has become a strategic imperative for modern computing infrastructure. Yet traditional design and verification methodologies are increasingly strained by escalating complexity, massive design scales, heterogeneous integration and rapidly evolving security threats. Ensuring correctness, scalability, comprehensiveness and adaptability across the full SoC lifecycle now exceeds the practical limits of conventional tool chains and human-centric workflows.

The emergence of LLMs introduces a transformative opportunity for SoC design automation. Beyond natural language understanding and code generation, advanced LLMs demonstrate capabilities in architectural reasoning, specification refinement, vulnerability analysis, and design-space exploration. Monolithic models alone are insufficient for the multidisciplinary and iterative nature of chip design. An agentic paradigm, where specialized LLM-driven agents collaborate within a coordinated framework, enables modular reasoning, cross-layer verification, security validation and adaptive decision-making throughout the design process.

Julie Rogers
Executive Director
The ESD Alliance, a SEMI Technology Coalition

Also Read:

Podcast EP355: An Overview of the Q126 Electronic Design Market Data Report with Wally Rhines

Agentic AI and the Future of Chip Design: From Productivity Tool to Engineering Partner

SemiWiki Q&A with Julie Rogers, Executive Director, ESD Alliance