Hot Chips 2026, formally the thirty-eighth Symposium on High Performance Chips, arrives at Stanford’s Memorial Auditorium from August 23 through 25 with a program that captures a decisive shift in computer architecture. Peak arithmetic throughput remains important, but the conference is increasingly about system balance: moving models and activations through memory hierarchies, scaling coherent chiplets, interconnecting accelerator racks, and controlling energy per generated token. The hybrid event opens with tutorials on memory technology and RISC-V, followed by two days of CPU, GPU, automotive, FPGA, memory, networking, and AI-accelerator disclosures.
Two SemiWiki sponsors will be attending this year: Agentrys and Quadric. I will be there as well. This is one of my favorite conferences, even more so now that AI has entered the picture.
HotChips draws a uniquely focused group of processor designers and SoC architects to present and discuss leading edge CPU, GPU and NPU architectures and their companion compilers. That group of almost 1000 renowned processor gurus is precisely the audience Quadric needs to reach to spread the word about the tensor-native Chimera GPNPU architecture. When chip and processor architects gather, Quadric wants to be there!
Agentrys believes that a purpose-built multi-agent system for chip design shouldn’t be a quarter-long project. Agentic AI systems are becoming quite popular to cut design time and increase quality for complex chip design projects. The challenge is finding the right agentic flow for a particular application. There are many offerings on the market to address this need, but most focus on a pre-built flow. If the flow isn’t exactly what’s needed, design teams are faced with long on-boarding to customize the flow. Some opt to build their own flow from scratch.
Agentrys has taken a different approach to address this need. Using the company’s Agentrys Studio Platform, building an initial agentic AI flow takes about 30 minutes. The company is showing real case studies of how Agentrys Studio cuts the problem down to size at two events. There will be live demos of an agentic AI design flow at the upcoming Hot Chips Conference, to be held in Palo Alto, CA from Sunday, August 23 – Tuesday, August 25, 2026. And the company will conduct a webinar to take you through the process of creating a different agentic AI design flow on Tuesday, September 15, 2026.
These are two opportunities to witness a revolution in agentic AI design flow development. Here are some details about both events as Agentrys shows you how to build a multi-agent system in 30 minutes.
Back to Hot Chips
The CPU sessions illustrate how general-purpose processors are being redesigned around heterogeneous data-center workloads. IBM will discuss a future Z and LinuxONE processor paired with an AI-inference acceleration chipset, while Intel will present Wildcat Lake and its next-generation Xeon, Diamond Rapids. NVIDIA’s Vera CPU, Fujitsu’s Arm-based MONAKA, and Arm’s disaggregated AGI server SoC broaden the architectural comparison. Particularly significant is Arm AGI’s emphasis on chiplets, scalable coherency, and terabyte-per-second memory bandwidth: these features indicate that socket architecture is becoming a fabric problem as much as a core-design problem.
The GPU program is equally forward-looking. NVIDIA’s Rubin targets agentic AI, AMD separates its Instinct MI400 discussion into GPU microarchitecture and system architecture, and Intel positions Crescent Island for inference. That division between device and system is technically revealing. Modern accelerator performance depends on HBM capacity and bandwidth, package-level die integration, collective communication, software-visible precision formats, and thermal envelopes. FLOPS without sufficiently provisioned data movement become stranded capability, especially during memory-bound autoregressive decoding.
Memory therefore receives first-class treatment. The Sunday tutorial spans HBM base-die logic, advanced HBM packaging, three-dimensional DRAM acceleration, and evolving AI memory architectures. Tuesday adds Samsung’s LPDDR5X processing-in-memory solution and XCENA’s MX1 CXL computational-memory device. Both approaches attack the energy and latency cost of transferring operands to distant compute. PIM can exploit internal bank bandwidth for inference kernels, while CXL devices can expand composable capacity and place computation near shared data. Their practical value will depend on programmability, coherency semantics, precision support, utilization, and integration with existing runtimes.
Networking presentations extend the same argument to rack scale. Broadcom’s Thor Ultra Ethernet NIC, NVIDIA’s BlueField-4 and Spectrum-X multiplane architecture, and Mojo Vision’s micro-LED optical I/O address congestion, isolation, orchestration, and bandwidth density. As training and serving domains grow, tail latency and collective efficiency can dominate nominal accelerator speed. The conference consequently treats the network as part of the machine rather than an external peripheral.
The AI sessions provide the broadest architectural diversity. Meta will describe custom silicon spanning recommendation and generative AI; Microsoft will present the MAIA 200 accelerator as part of a data-center-scale system; Cerebras will explain rack-scale deployment of its wafer-scale engine; SambaNova will detail the SN50 reconfigurable dataflow unit; and Google will disclose an eighth-generation TPU family split between training and serving. NVIDIA’s LPU talk and OpenAI’s presentation further emphasize workload-specific design and the shortening path from model requirements to silicon.
Automotive computing supplies a useful counterpoint. Waymo’s keynote and sensor-fusion processor, alongside BOS Semiconductors’ chiplet-based Eagle-N SoC, must reconcile throughput with deterministic latency, functional safety, harsh power limits, and continuous sensor ingress. These constraints expose weaknesses that data-center benchmarks can hide.
The poster program reinforces this breadth, covering open-source silicon education, multimodal edge platforms, a twenty-chiplet inference package, photonic tensor processing, event-driven graph acceleration, coarse-grained reconfigurable arrays, thermodynamic CMOS computing, and embodied-agent navigation hardware for real-time robotics deployments.
Bottom Line: Taken together, the advance program suggests that Hot Chips 2026 will be less a parade of isolated dies than a survey of integrated computing systems. The central engineering question is how to deliver useful, reliable performance when transistors, memory, interconnect, packaging, cooling, and software must scale together. Its most consequential disclosures should therefore be evaluated not by peak specifications alone, but by sustained utilization, bandwidth per watt, latency under load, deployment complexity, and the quality of the complete hardware-software stack.
I hope to see you there!
Also Read:
Meet Quadric on the Road: Three Must-Attend AI Events
Beyond Moore: Co-Optimizing AI from Systems to Materials
Podcast EP361: An Overview of the AI Infra Summit with Ed Nelson
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