proteanTecs Addresses Growing Power Consumption Challenge with New Power Reduction Solution

proteanTecs Addresses Growing Power Consumption Challenge with New Power Reduction Solution
by Mike Gianfagna on 02-06-2024 at 6:00 am

proteanTecs Addresses Growing Power Consumption Challenge with New Power Reduction Solution

proteanTecs is a unique company, delivering electronics visibility from within. Its core mission is to enable the electronics industry to continue to scale. The company achieves this goal by first embedding on-chip monitors, called Agents, during the design process to generate deep data on the chip’s profiling, health, and… Read More


2024 Outlook with Steve Roddy of Quadric

2024 Outlook with Steve Roddy of Quadric
by Daniel Nenni on 01-29-2024 at 10:00 am

Man on Llama

Quadric Inc. is the leading licensor of general-purpose neural processor IP (GPNPU) that runs both machine learning inference workloads and classic DSP and control algorithms.  Quadric’s unified hardware and software architecture is optimized for on-device ML inference. I have know Steve Roddy for many years, he is a high … Read More


Andes Webinar (China) – Releasing All Potential of RISC-V: Total Solutions of Andes Core Processors Series

Andes Webinar (China) – Releasing All Potential of RISC-V: Total Solutions of Andes Core Processors Series
by Admin on 01-15-2024 at 4:28 pm

Description

Join us for an engaging webinar as we delve into the boundless possibilities of RISC-V architecture with a focus on the comprehensive Total Solutions offered by the Andes Series. Explore how these cutting-edge RISC-V CPU cores are reshaping the landscape of computing, powering innovations across diverse applications… Read More


Webinar: Deep Dive into the UVM Register Layer: User-Defined Doors, Predictors, and Callbacks

Webinar: Deep Dive into the UVM Register Layer: User-Defined Doors, Predictors, and Callbacks
by Admin on 10-25-2023 at 3:57 pm

This webinar focusses on three specific aspects of the UVM register layer that will help you to model in UVM some of the less obvious ways in which registers can behave, such as non-linear addressing, burst access mode, registers accessed through an embedded CPU and quirky registers.

The following topics will be covered:

  • Using
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Webinar: FPGA Design Verification in a Nutshell Part 1: Verification Planning (US)

Webinar: FPGA Design Verification in a Nutshell Part 1: Verification Planning (US)
by Admin on 08-07-2023 at 4:51 pm

Time: 11:00 AM – 12:00 PM (PDT)

Abstract

As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and… Read More


Webinar: FPGA Design Verification in a Nutshell Part 3: Advanced Verification Methods (US)

Webinar: FPGA Design Verification in a Nutshell Part 3: Advanced Verification Methods (US)
by Admin on 08-07-2023 at 4:49 pm

Time: 11:00 AM – 12:00 PM (PDT)

Abstract

As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and… Read More


Webinar: FPGA Design Verification in a Nutshell Part 2: Advanced Testbench Implementation (US)

Webinar: FPGA Design Verification in a Nutshell Part 2: Advanced Testbench Implementation (US)
by Admin on 08-07-2023 at 4:48 pm

Time: 11:00 AM – 12:00 PM (PDT)

Abstract

As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and… Read More


Webinar: Cloud Enabled Simulation- Ansys Gateway Powered by AWS

Webinar: Cloud Enabled Simulation- Ansys Gateway Powered by AWS
by Admin on 02-06-2023 at 1:57 pm

Simulation is more accessible than ever, and unlocking its full potential will deliver innovation and results. Are you restricted by CPU or GPU counts? Do you find your team sacrificing quality or speed depending on the project and priorities? How can Ansys Gateway help?

Join us as we discuss what our customers are … Read More


Achronix on Platform Selection for AI at the Edge

Achronix on Platform Selection for AI at the Edge
by Bernard Murphy on 01-30-2023 at 10:00 am

Edge compute

Colin Alexander ( Director of product marketing at Achronix) released a webinar recently on this topic. At only 20 minutes the webinar is an easy watch and a useful update on data traffic and implementation options. Downloads are still dominated by video (over 50% for Facebook) which now depends heavily on caching at or close to … Read More


Webinar: Using Formal Datapath Validation to Verify AI Processor Computations hosted by Synopsys

Webinar: Using Formal Datapath Validation to Verify AI Processor Computations hosted by Synopsys
by Admin on 12-14-2022 at 1:46 pm

Summary

For over a decade, CPU and GPU design companies have been using Synopsys VC Formal Datapath Validation (DPV) app with its HECTOR™ technology to verify their data processing elements because traditional verification methods cannot exhaustively verify the correctness of mathematical computations in these designs.

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