The Invisible Bottleneck Is Costing You Time You Can’t Get Back

By Joel Jorgensen, FlowAccel.

The 2026 Siemens EDA and Wilson Research Group study just came out. Verification now eats close to half the schedule on every IC and FPGA program. I don’t doubt that number. What I don’t know is how much of it is actually verification, and how much of it is something else showing up disguised as verification.

Sometimes the technical problem really is the bottleneck. More often than you’d think, it’s the workflow.

Bottlenecks in delivering silicon products happen for many reasons, but one class of causes stays invisible. It stays invisible because we don’t look for it, and we don’t design it out the way we design bugs out of a circuit or code. We deal with it only once the impact is high enough, but it’s rarely a real focus area for silicon development teams. We aren’t alone. This challenge is pervasive across every industry and every business. It isn’t taught in MBA or engineering programs, and not much has been published about designing it out of any industry.

Workflow defects are the invisible bottleneck. Defects push out tape-in dates. Defects eat your engineers’ time. A workflow defect is simply something that didn’t go right while the work was happening. You needed data on Tuesday; you got it Thursday. The upstream team handed the downstream team the wrong data, so work stops until it gets fixed. A tool changed, and now people don’t know how to use it properly. The information capturing a bug is not clear, so debugging stops until it’s clarified. The list is endless.

Defects exist in workflows because of change, increasing complexity, and neglect. Even though we run into them constantly, they’re rarely fixed so they don’t come back. We do this for our products. We don’t do it for our work processes. When we design a development flow, we think about phases, milestones, and integration points. We think like an architect, and once we have the outline, we start building the product. Ready, fire, aim.

I was leading a post-silicon design team for a new NAND device. We had reps from every function ready, all of us eagerly waiting for that first wafer to show up in the lab. Day or night, any day of the week, we had a plan to start checkout the moment it arrived.

It arrived, and we dug in. We met every morning to align on priorities, because first silicon is chaotic no matter how much you plan for it. Things were going well. The part wiggled; it was functional, and we could read, write, and erase flash cells. We started implementing features we pushed to post-silicon. We enabled more tests for product engineering. The goal of post-silicon design is to put product engineering and the fab in the critical path, and by getting there, the design was doing exactly what it was built to do. Now we had to figure out how to make it yield and ramp.

Eventually it was time to stop making changes. The plan was to finish our wafer-level data collection, verify and validate the changes, close out the layout changes, run the back-end flows like ERC and DRC, and send the database to the mask shop.

The plan didn’t happen. Eventually, the program manager was in my cube asking why we were late for our first stepping. We’d been working long hours, some nights and weekends, but I didn’t have a good enough answer. I didn’t know what was taking us so long.

I leaned on a tool I’d used in the factory when I was NPI Chair, the one that helped us deliver a 22-day lead lot when our best to date was 35 days. We mapped our design workflow the same way we mapped process flow in the factory, trying to find out why we were three weeks late against a five-week schedule. Not a comfortable place to be as a leader. I could feel the whole organization’s eyes on our team, and on me.

The mapping showed our pre-silicon validation flows were too slow for post-silicon. In pre-silicon, we had months between milestones, so a seven-day cycle time for a full data turn was fine. We ran three validation passes at the end to clean up the design. That’s 21 days right there.

We redesigned the work to meet the schedule. I challenged the team to get a validation turn down to three days, because that’s what my calculations said we needed to hit the five-week cycle. I can still see their faces when I told them that; I think they thought I was crazy. But we dug in. First: automation, automation, automation. We had to remove manual review of simulation data and silicon data. We negotiated with our pre-silicon partners for the fastest servers for our simulations, then borrowed most of their licenses for our final validation push. We made a dozen other changes, and eventually landed a workflow with a 3.5-day validation cycle time. Over the next couple of steppings we dialed it in, and for the ten steppings after that, we hit the five-week date like clockwork.

On the surface, this looks like a typical silicon engineering problem. But look again at what actually happened. We knew how to do checkout, analog design, logic design, data path design, physical layout, and how to fracture the database for the mask shop. What we hadn’t done was design the work itself so all of that could happen inside five weeks. Relative to that five-week cycle, dozens of workflow defects stood in our way. Removing them cut our validation cycle time in half.

Toward the end of my career, removing defects from our development flow became my job, one way I helped scale our SSD business. Since then, I’ve seen hundreds of these maps across every domain: PCB, qual, ASIC design, firmware design, packaging, product life cycle, customer engineering, marketing, finance, and supply chain. Working in silicon product development is complicated, and it never stops changing.

Workflow defects are the invisible bottleneck to delivering silicon products and to scaling product development operations. In a complex, changing world, work is getting harder, the same way the products themselves are. Increasing complexity and change are seeping into our workflows, slowing teams down and consuming resources we don’t have to spare.

My recommendation: design your work the way engineers design products. Intentional. Functional. Synchronous. With a fast clock.

Don’t let the invisible bottleneck cost you time you can’t get back.

Joel Jorgensen founded FlowAccel, helping silicon systems engineering leaders deliver on roadmap commitments and scale development organizations. During 25 years at Intel, he spent 15 years in analog design and architecture for non-volatile memory technologies, earning two patents and co-authoring two IEEE ISSCC papers. He also served as an NPI Chair in manufacturing and later led efforts to expand the use of Steven Spear’s High Velocity Edge methodology beyond Intel’s SSD organization, including bringing Spear in to work directly with Intel engineering leadership.

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