TSMC’s 2026 OIP Forum to Spotlight the Technologies Shaping the Next Era of Chips

It’s that time of year again. Time certainly flies when AI is chasing you! This year marks the 18th TSMC OIP Ecosystem Forum, and it promises to be bigger and better than ever. My SemiWiki partners, Mike Gianfagna and Kalar Rajendiran, will join me in covering the event live, so stay tuned for all the news that’s fit to print.

Mike and Kalar previously worked at eSilicon, which was both a major SemiWiki sponsor and a TSMC Value Chain Aggregator. Kalar also manages the SemiWiki IP Reports. It really is a small semiconductor world.

TSMC will bring together semiconductor designers, technology partners, customers, analysts and media for its 2026 North America Open Innovation Platform Ecosystem Forum on Wednesday, September 23, at the Santa Clara Convention Center in California. Running from 9 a.m. to 2:30 p.m. Pacific Time, the event will examine how advances in silicon processes, chip packaging, artificial intelligence and electronic design tools are changing the way increasingly complex integrated circuits are built.

The forum’s theme, “Expanding AI with Leadership Ecosystem,” reflects the growing importance of collaboration across the semiconductor industry. Modern chips are no longer created through manufacturing innovation alone. Their development depends on a closely connected network of foundries, design-software providers, intellectual-property suppliers, cloud platforms, packaging specialists and customers. TSMC’s Open Innovation Platform, or OIP, is intended to bring those capabilities together and make them available through validated, production-ready design solutions.

Next-generation process technology will be a central topic. Presentations will cover design flows, methodologies and tools supporting TSMC’s N2, A16 and A14 processes, with particular attention to energy efficiency, multiphysics effects and advanced chip architectures. Attendees will also receive updates on the continuing development of tools and solutions for established and forthcoming advanced nodes, including N3, N2 and processes beyond them.

Advanced packaging will receive comparable attention. The program will explore design solutions for TSMC’s 3DFabric portfolio, including InFO, CoWoS, SoIC and SoW technologies, as well as TSMC-COUPE. These technologies allow companies to combine multiple computing, memory and connectivity components within sophisticated packages or three-dimensional systems. This approach has become increasingly important as developers seek higher performance without depending exclusively on traditional transistor scaling.

The forum will also examine the use of agentic AI in semiconductor design. TSMC’s ecosystem partners are expected to demonstrate how more autonomous AI workflows can improve productivity and optimize both conventional two-dimensional chips and complex 3D integrated circuits. Additional sessions will address solutions tailored to high-performance computing, AI and machine learning, automotive systems, mobile devices and the Internet of Things. Specialty platforms covering ultra-low-power, ultra-low-voltage, analog, radio-frequency and millimeter-wave technologies will round out the technical program.

The agenda begins with registration and breakfast at 8:30 a.m., followed by welcome remarks at 9:30. TSMC keynotes and a guest speech will run until 11 a.m. Afterward, TSMC and OIP partners will lead technical sessions. The event also includes the OIP Partner of the Year Award luncheon and an afternoon visit to the ecosystem pavilion, where participants can examine partner technologies and solutions. Customer case studies will illustrate how collaboration, semiconductor IP and cloud-based design environments can shorten development cycles and accelerate products’ arrival in the market.

Why does this matter? The semiconductor industry is confronting several challenges at once. AI systems require enormous increases in computing and memory performance, but power consumption, heat, manufacturing complexity and development costs are also rising. No single company can solve all of those problems independently. Progress increasingly depends on whether manufacturing processes, design tools, reusable IP and advanced packaging technologies work together reliably.

The OIP Forum therefore serves as more than a showcase for individual technologies. It offers a view of whether the broader design ecosystem is ready to turn ambitious process and packaging roadmaps into manufacturable products. Updates involving N2, A16 and A14 may help indicate how designers will access future gains in performance and efficiency. Developments around CoWoS, SoIC and other 3DFabric technologies are especially relevant to AI accelerators, where closely integrating processors and high-bandwidth memory has become critical.

Bottom line: The attention given to agentic AI is equally significant. If these workflows prove dependable, they could help engineering teams explore more design options, identify problems earlier and manage the growing complexity of 2D and 3D systems. Ultimately, the forum matters because the innovations discussed there may influence the cost, speed and energy efficiency of future computing products—from data-center AI hardware and vehicles to smartphones and connected devices.

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