TSMC OIP Ecosystem Forum 2026: Broadcom’s View of ASICs and Ecosystems

I spent a significant part of my career in the ASIC business. This segment of semiconductors has always been challenging, difficult and invigorating. There is something special about delivering a working custom chip that enables your customer to bring a world-changing product to market. It has always been a highly competitive business. For many years, I recall Broadcom being the one to beat. The combination of a vast library of proven IP from its broad product portfolio (especially its SerDes) and the deep design skills that came from the LSI Logic acquisition made the company hard to beat.

At this year’s TSMC OIP Ecosystem Forum, Broadcom took the stage for the second keynote address of the event. I found it fascinating to get a close look at what makes the Broadcom ASIC engine tick. There were some familiar topics around superior IP and design methodology, but there were also some new items of interest. The way Broadcom works with the larger ecosystem, especially TSMC described an important margin of victory. Let’s look closer to better understand Broadcom’s view of ASICs and ecosystems at TSMC OIP 2026.

Solving Today’s XPU Challenges with Tomorrow’s Solutions

That was the general topic of this keynote, presented by Greg Dix, Vice President of Engineering, ASICs Product Division at Broadcom. Greg painted a diverse and colorful picture of the ASIC business and what it takes to win in such a demanding market.

He touched on many topics, including IP, process, materials, integration and methodology. What was most interesting to me is how Broadcom views the broader ecosystem. Relationships with companies such as TSMC play an important role in its market dominance.

Here are some of the key points offered by Greg during his keynote.

As AI chips become larger, faster, and vastly more complex, Broadcom is betting that the winners will be those who solve tomorrow’s engineering problems before customers even encounter them.

The race to build the next generation of AI computing is no longer simply about making a faster chip.

It is about integrating enormous amounts of compute, memory, connectivity, and packaging into systems so complex that many of the technologies needed to build them must be invented years before the final product reaches the drawing board.

That was the central message of Broadcom’s keynote –

“Roadmap the Future: Solving Today’s XPU Challenges with Tomorrow’s Solutions”

The company’s view is straightforward: in custom silicon, winning the next major XPU program requires more than delivering today’s technology. It requires anticipating what customers will need several generations from now—and having those capabilities ready when the opportunity arrives.

That challenge is especially important in the ASIC market.

Unlike a general-purpose processor where customers largely accept a predetermined set of features, performance targets, and design tradeoffs, an ASIC starts with the customer’s workload and objectives. The customer determines what it wants; Broadcom’s task is to assemble the right mix of process technology, IP, memory, connectivity, packaging, and design methodology to make that vision possible.

That flexibility is powerful, but it dramatically raises the stakes.

New semiconductor technologies often require two or three years to develop and qualify. By the time a customer needs an advanced capability, it may already be too late to begin developing it. Broadcom therefore places multiple technology bets in parallel, evaluates them aggressively, and abandons approaches that fail to deliver sufficient value.

The objective is not merely to win a design. It is to become what Greg described as an “enduring incumbent”—a partner customers return to because previous commitments were delivered. A supplier can win once by promising an aggressive schedule, technology, or price. Winning repeatedly requires something harder, execution.

That pressure has fundamentally changed Broadcom’s approach to technology adoption. In earlier semiconductor generations, the company could wait until a process was mature, models were stable, and manufacturing risks were understood. AI accelerators no longer permit that luxury. Broadcom has moved from being a fast follower to an early adopter, working with partners such as TSMC while technologies are still evolving.

The advantage is not simply speed. Early adopters can help shape emerging technologies around the needs of future products. Nowhere is that evolution more visible than in advanced packaging.

AI processors have expanded from large monolithic dies connected to conventional memory into sophisticated assemblies containing multiple compute dies, I/O chiplets, high-bandwidth memory, interposers, and increasingly, vertically stacked silicon. Instead of placing every function on the most advanced—and most expensive—process node, designers can disaggregate the system and place different functions on the technologies best suited to them.

Broadcom sees 3D integration as the next major step.

Stacking dies introduces an entirely new set of engineering problems: delivering power through multiple layers of silicon, extracting heat from stacked structures, performing timing analysis across dies manufactured on different process nodes, testing individual components before expensive assembly, and managing an enormous increase in design compute requirements.

The solution is to address these problems before the customer design begins.

Greg described an extensive program of mechanical, thermal, electrical, and risk-mitigation test vehicles intended to validate new technologies ahead of production. These platforms allow engineers to study everything from package warpage and thermal behavior to SerDes performance, HBM operation, routing, and system-level integration.

The goal is what Greg repeatedly called “first-time-right” silicon.

For today’s largest AI accelerators, a silicon re-spin can mean far more than an engineering delay. It can mean missing the market entirely.

That reality is also reshaping design methodology. Broadcom expects development to become increasingly concurrent: process technology, packaging, IP, design tools, and customer products evolving at the same time rather than sequentially.

Artificial intelligence itself will accelerate that transformation. Broadcom expects AI-driven design techniques to compress implementation schedules even further, placing increasing pressure on backend design, verification, compute infrastructure, and methodology.

Greg pointed to a recent large XPU program that moved from kickoff to tapeout in roughly nine months—an illustration of how quickly expectations are changing.

Yet perhaps Greg’s most important message was not about any individual technology.

It was about collaboration.

Future XPUs cannot be designed in isolation. Success will depend on semiconductor companies working closely with foundries, memory suppliers, packaging houses, EDA vendors, equipment providers, and customers—often while the underlying technologies themselves are still being developed.

Greg explained that Broadcom’s philosophy is that “hard problems are a good thing.”

He pointed out there will be plenty of them ahead. AI systems will demand more compute, more memory bandwidth, larger packages, faster interconnects, improved thermal solutions, and increasingly sophisticated integration.

For semiconductor companies, those challenges create risk—but they also create differentiation.

And in Broadcom’s view, the companies that solve those problems before the market needs the answers will be the ones positioned to win the next generation of AI silicon.

To Learn More

Greg’s keynote touched on many key trends and market requirements, but the complete story is much larger. You can explore a larger view of Broadcom’s capabilities here. And that’s Broadcom’s view of ASICs and ecosystems at TSMC OIP 2026.