Beyond the Die: Verifying the Connected Chip

One of the standout presentations at the 2026 TSMC OIP Forum highlighted a collaboration between Siemens EDA, Marvell, and TSMC. I always appreciate EDA presentations that bring together customer and foundry perspectives, and this one did not disappoint. We follow 3D IC technology closely and have published more than 150 blogs on the topic over the past three years. As chiplet adoption accelerates, I fully expect SemiWiki to publish twice that many over the next three, absolutely.

Advanced packaging is changing what it means to verify a chip. As semiconductor designers assemble multiple dies into increasingly complex systems, reliability can no longer be established by checking each component independently. The presentation, “Efficient, Scalable Methodology for Reliability and ESD Verification of Complex 3D IC CoWoS Systems” describes how Marvell and Siemens are addressing that challenge through automated verification of the complete assembly.

The shift reflects a broader change in semiconductor architecture. Instead of placing every function on one large die, designers can distribute functions across smaller dies, selecting technologies suited to each task. TSMC’s Chip on Wafer on Substrate, or CoWoS, technology supports this approach. The potential benefits include improved performance, lower power consumption, better manufacturing economics, and greater flexibility in combining different technologies.

But dividing a design creates new dependencies. Electrical connections now extend through dies, bumps, interposers, and substrates. A component that passes its own verification checks may still participate in an unsafe protection path once assembled with other components. The essential question becomes whether the entire system works together under the conditions its protection circuitry must withstand.

Electrostatic discharge, or ESD, illustrates the problem. Protection structures must provide suitable paths for discharge current, with sufficiently low resistance and adequate current carrying capacity. In a multidie assembly, the structure protecting a vulnerable circuit may reside on another die. Different dies can also have different protection schemes, manufacturing processes, and ESD requirements. Their individual qualifications therefore cannot substitute for checking the assembled protection network.

The methodology presented combines individual die verification with system level analysis. Each die is first checked using Siemens Calibre PERC and applicable foundry rule decks. Assembly information then supports Calibre 3D PERC checks across the integrated system. This preserves the value of established die verification while extending analysis to the connections and interactions introduced by advanced packaging.

Three areas receive particular attention: protection topology, point to point resistance, and current density. Topology checks establish whether required protection structures exist and connect as intended. Resistance checks assess whether discharge paths meet specified limits. Current density analysis evaluates whether the interconnect can carry the required current without exceeding its allowable capacity. Together, these checks address both the organization of the protection network and the physical adequacy of its paths.

Scale makes automation essential. One package ball can connect through multiple bumps and branches, producing many possible paths to analyze. Including substrate, interposer, and die contributions increases computational complexity. Engineers also need debugging tools that identify which layers or connections contribute to a violation, so they can locate the cause and make an informed design change.

The speakers describe an earlier workflow involving separate die checks, manual interface verification, and manual debugging that could take two to three weeks. Their automated approach brings die and assembly information into a holistic verification flow. The transcript does not provide a measured replacement runtime, but it clearly identifies the objective: reduce manual effort and improve the consistency of complex system checks.

Why this matters extends beyond verification productivity. AI infrastructure depends on powerful compute systems and the high bandwidth connections that allow accelerators to cooperate. Advanced packaging helps enable those systems, but integration also concentrates value and risk within each assembly. A protection failure can compromise a package containing multiple otherwise functional dies.

The presentation’s hypothetical yield example makes that exposure tangible. If ten components each have a 99 percent success probability, their combined probability is roughly 90 percent, assuming independent outcomes. This illustrates compounding risk, rather than predicting manufacturing yield. It reinforces the need to catch integration problems early. Finding those problems before fabrication can also prevent costly redesigns and protect schedules for products with demanding requirements.

Bottom line: The broader lesson is organizational as well as technical: reliability and ESD specialists should participate from the beginning. Effective verification requires rules matched to the assembly, clear protection requirements, and visibility across component boundaries. As chips become systems, verification must follow.

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