Siemens and TSMC push AI deeper into chip design

Siemens and TSMC are expanding their collaboration on semiconductor design tools, with a focus on AI assisted workflows, advanced chip packaging and support for newer manufacturing processes. Their announcement centers on an AI agent intended to find and fix design rule violations: errors that can prevent a chip layout from being manufactured as planned.

The proposed workflow connects Siemens’ Calibre verification software with its Aprisa and Solido design tools. Instead of requiring engineers to diagnose every violation and make each correction by hand, the agent is designed to identify a problem, analyze its context, suggest or carry out a fix, and check the result. Siemens and TSMC say this could reduce manual work and shorten the path to tapeout, when a finished design is sent for manufacturing.

That is a meaningful target. Modern chips contain enormous numbers of features, and each new manufacturing process comes with detailed rules governing how those features can be placed and connected. A design may work in a simulation yet still fail a manufacturing check. Fixing one violation can also create another or affect power use, speed or chip area. Verification is therefore an iterative part of development, not a box engineers tick at the end.

The companies describe a broader ambition for Siemens’ Fuse EDA AI system: agents that can work through long, multistep tasks across several tools and validate their own outputs. The collaboration also covers custom chip design and the placement and routing of digital circuits. The practical question is how reliably these systems can handle real projects, where an apparently simple correction may have consequences elsewhere in the design. The announcement describes capabilities and expected benefits, but does not provide customer results showing how much time or cost they save.

The work extends beyond AI. Siemens says its tools support several TSMC process technologies and aspects of TSMC’s 3DFabric packaging platform. In 3D designs, engineers may stack chips or connect separate pieces of silicon, often called chiplets, within one package. Those choices introduce challenges involving connections between chips, signal quality and heat. Siemens reports expanded verification support for stacked designs, thermal analysis work and continuing development of chip and package design flows. Some capabilities have been certified for particular TSMC technologies; others remain under development or certification.

Why it matters

Chip design is becoming a coordination problem as much as a drawing problem. Engineers must balance performance, energy use, manufacturability, reliability and heat, often across multiple pieces of silicon. Advanced packaging can improve what a system can do, but it also creates more interfaces to check and more ways for one design decision to affect another. Better connected design and verification tools could help teams catch problems earlier, when changes are easier to make.

The collaboration also shows where AI may find a useful role in engineering. A design rule violation has a specific context and a result that can be checked with established software. That gives an AI agent a bounded task and a way to test its work. Even so, a passing check does not prove that a change is the best choice for the whole chip. Engineers will still need to judge trade-offs, especially when a fix affects timing, power or reliability.

There is an ecosystem effect, too. When design tools are certified for a manufacturer’s processes and packaging technologies, chip companies can use those flows with greater confidence. Siemens and TSMC are also extending training resources to TSMC design partners, which may help more teams learn the methods needed for advanced nodes.

Bottom line: For chipmakers, the value of this announcement will ultimately depend on measured results: fewer hours spent resolving violations, faster design cycles, and chips that meet their targets when manufactured. The companies have outlined an ambitious direction. The next test is whether these connected tools deliver those gains consistently on complex customer designs.

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