Detail-Route-Centric Physical Implementation for 7nm

Detail-Route-Centric Physical Implementation for 7nm
by Alex Tan on 10-10-2018 at 12:00 pm

For many years TSMC has provided IC design implementation guidance as viewed from the process and manufacturing standpoints. The last time TSMC Reference Flow incremented, it was version 12.0 back in 2011. Since then, increased design, process and packaging related complexities of the advanced nodes have demanded more focused… Read More


Aprisa and Apogee – The New Avatars

Aprisa and Apogee – The New Avatars
by Alex Tan on 07-19-2018 at 12:00 pm

Earlier physical optimization impacts a design QoR gain and can disclose potential hurdles in dealing with unknown design variants such as new IP inclusion or new process node issues. Along the RTL-to-GDS2 implementation continuum, a left-shift move requires a robust modeling and proper context captures in order to produce… Read More


ATopTech is Back!

ATopTech is Back!
by Daniel Nenni on 09-18-2017 at 7:00 am

One of the biggest surprises at the TSMC OIP Forum last week was the reappearance of bankrupt EDA vendor ATopTech. I spoke with former ATopTech CEO and now Avatar IS President Jue-Hsien Chern at OIP. As a survivor of several EDA legal battles myself, I understand what ATopTech went through and I am thoroughly impressed that they had… Read More