Siemens CTO update on Calibre at DAC 2026

At DAC 2026 I had the opportunity to speak with Juan Rey, CTO Siemens EDA about the Calibre product used for IC physical verification, circuit verification, 3D IC and DFM optimization. Juan has been involved with Calibre since 2001, served on the Board of Directors of Silicon Integration Initiative (SI2), on the Executive Technology Advisory Board of Semiconductor Research Corporation (SRC), and on industry advisory boards of academic research centers, such as the Center for Domain-Specific Computing at UCLA.

What has set Calibre apart over the decades has been the engineering focus on ultimate quality, providing robust results that are reliable. To achieve this requires software engineers that can code for the best performance, short run times, and scalability all under a small memory footprint. Their dev team is constantly focusing on improvements and looking for new techniques to stay ahead of the growing IC physical verification challenges.

Semiconductor technology has steadily progressed: FinFET, GAA, Nanosheet, CFET. Advanced packaging has created 2.5D and 3D stacking of chiplets, creating new requirements for physical verification like thermal analysis, stress analysis and reliability analysis. Siemens EDA has the benefit of early access to the leading IC design customers and has introduced new products like Calibre 3DThermal and Calibre 3DStress to meet the new challenges.

Calibre 3DThermal can run accurate and efficient thermal analysis throughout the 3D IC design flow, ensuring that each chiplet in the assembly works electrically as specified. Tool users define the 3D stack-up and then the tool knows the connectivity and geometries used to analyze cross-die coupling effects, thermal and stress impacts.

With Calibre 3DStress a design team can manage thermal-mechanical stress by simulation and analysis during and after the packaging process, to identify and mitigate against warpage, cracking and mobility changes.

AI and ML technologies have been added inside of the Calibre products to help obtain faster results and improve workflows. For example, AI can help debug a Calibre run that reports millions of errors more quickly by automatically triaging errors into common groups and pointing out which errors are most important to fix first. AI is also used for improving the setup times of complex runs, making sure to most efficiently use hardware resources across diverse collections of CPU and GPU cores.

AI agents are being used in the IC design to help orchestrate on a common goal, finding out the source of errors, providing insight to fixing the error, then verifying the fix. Future designs become more efficient based on the learned experiences of previous designs.

Siemens has been providing the vision for using Digital Twins across multiple industries for over a decade now, and the Calibre team has embraced this core concept. A Digital Twin model needs to be dynamic, changeable, but always in sync with the design specification. EDA models are Digital Twins and the span covers chips, chips on boards, boards filling a rack in a data center, then how to keep everything running cool and reliable across workloads.

Summary

Talking with a long-time Calibre leader was a highlight of DAC 2026 for me, as I learned how focused their team is on constant innovation and solving new challenges in physical verification in a timely manner. Siemens has been able to introduce a stream of new products and features in their growing family of Calibre products over the years to stay relevant and in the technology lead.

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