From Custom Silicon to AI Systems: Why Cross-Layer Engineering Matters

The central argument of Ankur Gupta’s AI Infra Summit keynote is simple but consequential: the next leap in AI infrastructure will not come from improving chips, servers, cooling systems, or data centers independently. It will come from optimizing the connections among them. Siemens frames this as a journey “from custom silicon to AI systems”— designing compute foundations that make AI infrastructure scalable and efficient.

AI infrastructure is commonly discussed in terms of individual components: faster GPUs, denser memory, better networking, or more efficient cooling. Siemens’ central argument is more consequential: the next performance breakthrough will come from optimizing the connections among semiconductor design, packaging, computing systems, and physical facilities—not from improving any one layer in isolation. The keynote frames this as designing the compute foundations for scalable, efficient AI infrastructure.

That shift is necessary because modern AI hardware operates with extremely tight physical margins. Advanced-node chips run at approximately 500–750 millivolts, where changes in temperature or voltage can directly affect timing closure. Heat generated within a chip influences cooling requirements at the server-blade level, while ambient data-center temperature can constrain silicon performance. Traditional electronic design automation (EDA) treats many of these concerns as separate problems. At today’s operating limits, however, chip, system, and facility behavior form one coupled engineering problem.

Siemens proposes three critical connections.

The first is EDA to silicon. AI-native EDA applies accelerated algorithms, machine learning, and intelligent agents across semiconductor design workflows. According to the presentation, accelerated engines can produce speedups of up to 1,000 times, while smarter execution may deliver productivity improvements of 10–50 times. Aprisa AI, for example, combines a natural-language automation agent with an AI design explorer. The agent automates labor-intensive physical-design work, while the explorer searches implementation strategies for improved power, performance, and area.

The technical value extends beyond completing existing tasks faster. AI systems change rapidly, so silicon designed around yesterday’s workload may reach production poorly matched to current models. Workload-aware EDA can incorporate actual computational patterns and physical constraints earlier, allowing engineers to evaluate architectural choices before they become expensive manufacturing commitments.

The second connection is silicon to system. Advanced packages combine chiplets, interposers, substrates, memory stacks, power delivery, and cooling interfaces. Electrical, thermal, and mechanical effects interact: temperature changes material expansion; expansion causes warpage and stress; physical deformation can damage interconnects or degrade reliability. Siemens reports that warpage has caused yield losses exceeding 50% in some deployments, while thermal stress accounts for about 30% of field-reliability issues.

A comprehensive digital twin addresses this problem by integrating multiphysics models and simulation. Instead of discovering thermal hotspots, deformation, or mechanical stress during manufacturing or deployment, teams can predict them before fabrication. This matters because late-stage fixes may require package redesigns, new cooling hardware, or reduced operating power. Earlier simulation therefore improves yield, reliability, development time, and the usable performance of expensive accelerators.

The third connection is system to facility. Once hardware ships, much of the engineering intelligence used to design it traditionally disappears from operational workflows. Data-center teams then manage cooling using conservative settings and incomplete information. The presentation estimates cooling at 15–30% of total data-center ownership cost and notes that chips may include roughly 15% design margin because real workload conditions cannot be modeled precisely during development. Operators pay for that uncertainty through excess cooling, wasted power, and throttled compute.

Lifecycle sensors and operational digital twins can close this loop. Real-time temperature, power, workload, and equipment data can inform facility controls, while field behavior can feed back into future chip and system designs. Siemens’ Intelligence Center X architecture adds knowledge graphs, predictive modeling, industrial ontologies, agent development, and workflow orchestration, while remaining open to different clouds, models, data platforms, and enterprise systems.

Why does this matter? AI capacity is constrained not simply by access to GPUs, but by energy, cooling, manufacturing yield, reliability, and utilization. A nominally faster chip creates little value if it must be throttled, fails prematurely, or requires disproportionate facility investment. Cross-layer engineering turns these constraints into variables that can be modeled and optimized together. The strategic advantage is therefore continuity—from nanometer-scale transistors through packages and racks to meter-scale facilities, and from initial design through live operation. Connecting the real and digital worlds can make AI infrastructure faster, more predictable, and materially more efficient.

Contact Siemens

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