Wilson Survey Signals Need for New Understanding of Verification Success

Siemens has again sponsored a Wilson-led survey on the state of (functional) verification in the industry, and this time Harry Foster (Chief Scientist, Verification at Siemens) has condensed his major takeaways from the report. These are intriguing – particularly an apparent revolutionary change in first-silicon trends. Where an average of ~30% of designs claimed first silicon success over at least a decade, this metric has been dropping, the latest survey now showing 5%. At first glance this may seem cause for panic, but Harry’s analysis offers a more thoughtful view. More needs to be done of course, but more important are the root causes behind the trend.

Silicon respins are expensive and risk missing market windows. The established verification discipline has been to work hard to maximize coverage before committing to manufacturing, aiming for right first-time (first silicon), which should ensure that risks are minimized. As design complexities grow, we add more people power, compute cycles, abstraction methods and now AI-based advances. And yet we are still falling behind. What’s going on? Harry breaks this down into 5 primary factors.

Accelerator-based volumes are growing

AI/GPU and CPU cluster designs are all sensitive to problems which can be very difficult to expose pre-silicon. Coherency issues (cache and IO) are amplified in systems sharing memory between data collection, feature extraction, inference and working memory in the AI engine. Problems might not be exposed for billions of cycles but are still as fatal for a product launch as issues more easily caught in traditional verification.

Such designs are not just the next click up in complexity. AI architectures have become fundamentally more complex to manage PPA tradeoffs for billion-plus parameter models while delivering competitive response times in inference at acceptable power budgets.

Software is intimately linked to hardware

It used to be that you could draw a bright line between hardware and software functionality and largely verify these independently. But the line has become less bright and a lot fuzzier. Now we have controllers in secure boot IP and safety IP. We make have a mix of ISAs, some with custom extensions; AI engines host even more specialized datatypes and instructions. How to verify correct operation on a representative set of complex workloads across this complex mix of software and hardware has become much more challenging.

Synthetic tests, system level VIP, PSS abstractions, emulation and FPGA prototyping are partial answers, but they can’t verify far up into the software stack, except with the largest hardware accelerators. AI engines further amplify the difficulty of this task. Running a large model (a chatbot, image recognition, code creation) under data and latency sensitive conditions may induce races, lockups or errors that simply cannot be detected pre-silicon. We can keep pushing on this boundary but still not high enough to guarantee high reliability in AI operation.

Verification language mix

This is changing in interesting ways. Harry doesn’t see the mix as a contributor to low success rate, more likely a signal of how verification teams are responding to deal with complexity. System Verilog used to dominate for testbenches (in UVM). Now it is neck and neck with C/C++ and Python, while PSS is coming from behind but growing fast. He sees these trends reflecting increased interaction with software/firmware workloads, automation and system level debug.

Firmware, safety and security

Interesting that the survey showed significant growth in respins around each of these factors. For safety and security, secure control and interaction with the software stack and external communications (telemetry) for on board processors also presents challenges in ensuring high coverage through a representative set of possible threats/failures.

Altogether, a very interesting analysis, suggesting the verification problems space is now much bigger than the old school view that if the chip meets the spec you are done. Verification (and validation) engineers have never been short of ideas. I am sure we’ll see more creative ways to address these challenges.

Harry has written several white papers drawing on the survey. I have provided here a quick summary of his Five signals blog:

• 2026 Functional Verification Study: Executive findings
• Five signals from the 2026 functional verification study
• AI in functional verification: What the 2026 industry data reveals
• DTFT’s expanding role in software-driven silicon

Also Read:

Beyond the Die: Verifying the Connected Chip

Siemens CTO update on Calibre at DAC 2026

Siemens and TSMC push AI deeper into chip design