Comparison of TSMC CoWoS-S, CoWoS-R, and CoWoS-L

Chip-on-Wafer-on-Substrate, commonly called CoWoS, is an advanced packaging platform developed by TSMC. It allows processors, chiplets, and high-bandwidth memory stacks to be integrated within a single package. CoWoS has become especially important for artificial-intelligence accelerators and high-performance computing systems, where processors need enormous memory bandwidth and fast die-to-die communication. The platform has three major variants: CoWoS-S, CoWoS-R, and CoWoS-L. Their main difference is the structure used to connect the components.

CoWoS-S is the original and most mature variant. The “S” refers to its silicon interposer, a large piece of silicon positioned beneath the logic chips and HBM stacks. Fine metal connections fabricated in the interposer provide very dense routing between these components. Through-silicon vias carry electrical signals and power vertically through the interposer to the package substrate.

The principal advantage of CoWoS-S is its excellent electrical performance. Silicon manufacturing supports very fine wiring, enabling high connection density, low latency, and efficient data transfer. Embedded deep-trench capacitors can also stabilize power delivery to demanding processors. These characteristics make CoWoS-S suitable for high-end products requiring predictable performance and extremely wide memory interfaces. Its technology and manufacturing processes are also well established.

However, producing a very large silicon interposer is difficult and expensive. As AI processors grow and incorporate more computing dies and HBM stacks, the required interposer may exceed the dimensions of a conventional lithography reticle. TSMC can combine exposures using mask stitching, but manufacturing complexity and the possibility of defects increase with interposer size. These constraints make continued scaling challenging.

CoWoS-R replaces the large silicon interposer with a redistribution-layer interposer. This structure uses layers of copper wiring and polymer dielectric material to connect the components. Because it does not depend on one large silicon die, an RDL interposer can be expanded more easily to support larger packages. It is also mechanically flexible, which can reduce stress and improve the integrity of package connections.

The trade-off is that CoWoS-R generally has less routing density than CoWoS-S. Its wiring dimensions are larger, so it may not be ideal for the most demanding short-distance die-to-die interfaces. Nevertheless, it provides good signal and power integrity and can be attractive for large HPC systems that prioritize package scalability, design simplicity, and potentially lower manufacturing cost. CoWoS-R entered volume production in 2023.

CoWoS-L combines features of both approaches. It uses an RDL-based interposer for broad package-level routing while embedding small pieces of silicon called local silicon interconnects, or LSIs, at selected locations. These silicon bridges provide dense connections between adjacent logic dies or between processors and memory where the highest bandwidth is needed. Less critical connections can travel through the surrounding RDL structure.

This hybrid design gives CoWoS-L an important balance. It approaches the connection density and electrical performance of CoWoS-S in critical areas without requiring a single enormous silicon interposer. At the same time, it retains much of the scalability and flexibility associated with CoWoS-R. CoWoS-L can also incorporate embedded deep-trench capacitors and other specialized components to improve power delivery and package functionality.

CoWoS-L is therefore particularly well suited to the direction of modern AI hardware. Future accelerators may contain several computing chiplets, larger numbers of HBM stacks, and increasingly complex communication networks. A full silicon interposer may become impractical at these dimensions, while a pure RDL interposer may not provide sufficient density at every interface. The selective placement of LSIs addresses both problems. TSMC began volume production of CoWoS-L in 2024 and is developing increasingly large implementations.

Bottom line: CoWoS-S offers the greatest maturity and consistently dense silicon routing but faces size and cost limitations. CoWoS-R emphasizes scalability, flexibility, and simpler large-package construction, with lower connection density. CoWoS-L provides a hybrid solution, concentrating silicon-level performance where it is most valuable while using RDL technology throughout the rest of the package. Consequently, CoWoS-L is emerging as the most promising option for very large, next-generation AI accelerators, although all three variants remain useful because different products have different performance, cost, and manufacturing requirements.

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