At the 2026 OIP Ecosystem Forum, the industry narrative shifted from incremental scaling to what TSMC defines as the “Intelligence Revolution.” Akin to the 18th-century Industrial Revolution which transitioned human physical labor to mechanical power, the current era is augmenting human ingenuity through … Read More
Tag: cowos
Comparison of TSMC CoWoS-S, CoWoS-R, and CoWoS-L
Chip-on-Wafer-on-Substrate, commonly called CoWoS, is an advanced packaging platform developed by TSMC. It allows processors, chiplets, and high-bandwidth memory stacks to be integrated within a single package. CoWoS has become especially important for artificial-intelligence accelerators and high-performance computing… Read More
TSMC’s CoWoS Capacity to Double by 2028—and Rivals Will Still Win Orders
TSMC reportedly plans to double its Chip-on-Wafer-on-Substrate capacity from approximately 130,000 300mm-equivalent wafers per month at the end of 2026 to 260,000 by 2028. The estimate is not formal company guidance and should be treated as a supply-chain projection. Nevertheless, the direction is consistent with TSMC’s… Read More
TSMC’s 2026 OIP Forum to Spotlight the Technologies Shaping the Next Era of Chips
It’s that time of year again. Time certainly flies when AI is chasing you! This year marks the 18th TSMC OIP Ecosystem Forum, and it promises to be bigger and better than ever. My SemiWiki partners, Mike Gianfagna and Kalar Rajendiran, will join me in covering the event live, so stay tuned for all the news that’s fit to print.
Mike and… Read More
Comparing Advanced Packaging from TSMC, Intel Foundry, and Samsung Foundry
Advanced semiconductor packaging has become essential to improving computing performance as conventional transistor scaling grows more difficult and expensive. Instead of manufacturing an entire processor as one large monolithic die, chipmakers can divide it into smaller chiplets and combine logic, memory, input/output… Read More
HBM’s Vertical Ascent: Why Packaging Is Becoming the Heart of AI Memory
SK hynix’s Hot Chips 2026 presentation explains how High Bandwidth Memory (HBM) is evolving to meet the extraordinary memory requirements of artificial intelligence. Its central message is that future progress will depend not only on better DRAM circuits but also on advanced packaging, denser vertical integration, improved… Read More
Executive Interview with James Huang of AlChip
I had a chance sit down with James Huang, Director of Engineering at Alchip Technologies, to discuss the company’s recent multi-die packaging achievements and learn about Alchip’s next steps in pushing the boundaries of innovation for next generation AI ASIC.
James is acknowledged as a leading light in advanced node ASICs, based… Read More
The Memory Sector Is Becoming One of the Main Beneficiaries of the AI Boom
The explosive growth of artificial intelligence is transforming the semiconductor industry, and nowhere is this more evident than in the memory sector. AI training and inference workloads are fundamentally memory-intensive, driving unprecedented demand for advanced DRAM architectures, High Bandwidth Memory (HBM), and… Read More
imec IC-Link and TSMC 3DFabric Alliance Expansion Signals New Era of System-Level Scaling
imec announced that IC-Link by imec has joined the TSMC 3DFabric Alliance, a strategically important move that reflects the semiconductor industry’s transition from traditional monolithic scaling toward heterogeneous integration, chiplet architectures, and advanced packaging-driven system optimization. The partnership… Read More
AI Chip Design Moves Beyond Monolithic Silicon with Alchip 3DIC
Artificial intelligence processors are entering a new era. For more than two decades, semiconductor innovation was driven primarily by transistor scaling and process node shrinks. Today, however, AI infrastructure demands are growing faster than traditional Moore’s Law improvements can sustain. The industry is now shifting… Read More
