The Difference Between CoWoS-S and CoWoS-R

CoWoS-S and CoWoS-R are two versions of TSMC’s Chip-on-Wafer-on-Substrate advanced packaging platform. Both technologies are designed to combine high-performance processors, chiplets and high-bandwidth memory, or HBM, within a single package. This shortens the electrical connections between computing and memory components, enabling higher bandwidth and better energy efficiency than conventional packaging. Their main difference lies in the material and structure used for the interposer that connects the chips.

CoWoS-S uses a silicon interposer. The “S” therefore refers to silicon. Logic dies and HBM stacks are mounted on a large piece of silicon containing extremely dense metal wiring. Through-silicon vias, or TSVs, carry electrical signals and power vertically through the interposer to the package substrate beneath it. Because semiconductor manufacturing processes can create very fine wiring on silicon, CoWoS-S offers exceptionally high interconnection density. TSMC also integrates embedded deep-trench capacitors into the silicon interposer, helping stabilize power delivery for demanding processors.

These characteristics make CoWoS-S particularly suitable for systems requiring the highest possible communication density between processors and memory. Its mature silicon-based design has been in production since 2012 and has been widely used in high-performance computing and artificial-intelligence accelerators. TSMC states that current CoWoS-S technology can support silicon interposers as large as approximately 3.3 reticle sizes, or about 2,700 square millimetres.

However, manufacturing a very large silicon interposer is technically difficult and expensive. The interposer must be produced using wafer-fabrication equipment, and its dimensions are constrained by lithography, wafer processing, yield and mechanical considerations. As packages expand to accommodate more computing dies and HBM stacks, producing a single, defect-free silicon interposer becomes increasingly challenging.

CoWoS-R addresses this scaling problem by replacing the silicon interposer with a redistribution-layer interposer. The “R” refers to RDL. Instead of being formed from a solid silicon wafer, the interposer consists mainly of polymer dielectric layers and copper wiring. TSMC’s CoWoS-R entered volume production in 2023. Its RDL interposer presently supports routing with a minimum pitch of four micrometres, corresponding to copper lines and spaces of approximately two micrometres each.

The RDL structure is less rigid than silicon. Its mechanical flexibility helps absorb stresses caused by differences in thermal expansion between the chips, interposer and organic package substrate. This can improve the reliability of the C4 solder joints connecting the interposer to the substrate. TSMC research has shown that multiple RDL layers can act as a stress buffer and provide strong joint reliability in large heterogeneous packages.

CoWoS-R also offers greater package-size scalability. TSMC recommends CoWoS-R or CoWoS-L when the required interposer exceeds approximately 3.3 reticle sizes. The RDL platform can therefore be attractive for extremely large AI and HPC packages containing numerous chiplets or memory stacks. Its copper routing can provide good signal and power integrity, while avoiding the need to manufacture one enormous silicon interposer.

The trade-off is that CoWoS-R generally does not provide the same interconnect density or integrated capacitor capability as a full silicon interposer. CoWoS-S remains the stronger choice where maximum wiring density, mature performance and tightly integrated power-delivery features are the priorities. CoWoS-R is more appropriate where package size, mechanical flexibility, scalability and potentially simpler large-area manufacturing are more important.

Bottom Line: CoWoS-S prioritizes maximum interconnect density and electrical performance through a silicon interposer, whereas CoWoS-R prioritizes large-package scalability and mechanical flexibility through a polymer-and-copper RDL interposer. Both support advanced heterogeneous integration, but they solve different engineering challenges within modern AI and high-performance computing systems.

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