Comparison of TSMC CoWoS-S, CoWoS-R, and CoWoS-L

Comparison of TSMC CoWoS-S, CoWoS-R, and CoWoS-L
by Daniel Nenni on 09-22-2026 at 6:00 am

TSMC CoWos Packaging Comparison

Chip-on-Wafer-on-Substrate, commonly called CoWoS, is an advanced packaging platform developed by TSMC. It allows processors, chiplets, and high-bandwidth memory stacks to be integrated within a single package. CoWoS has become especially important for artificial-intelligence accelerators and high-performance computing… Read More


The Difference Between TSMC CoWoS-S and CoWoS-R

The Difference Between TSMC CoWoS-S and CoWoS-R
by Daniel Nenni on 07-31-2026 at 6:00 am

The Difference Between CoWoS S and CoWoS R

CoWoS-S and CoWoS-R are two versions of TSMC’s Chip-on-Wafer-on-Substrate advanced packaging platform. Both technologies are designed to combine high-performance processors, chiplets and high-bandwidth memory, or HBM, within a single package. This shortens the electrical connections between computing and memory components,… Read More


Alphawave Semi Unlocks 1.2 TBps Connectivity for HPC and AI Infrastructure with 9.2 Gbps HBM3E Subsystem

Alphawave Semi Unlocks 1.2 TBps Connectivity for HPC and AI Infrastructure with 9.2 Gbps HBM3E Subsystem
by Kalar Rajendiran on 08-27-2024 at 10:00 am

9.2Gbps HBM3E Subsystem

In the rapidly evolving fields of high-performance computing (HPC) and artificial intelligence (AI), reducing time to market is crucial for maintaining competitive advantage. HBM3E systems play a pivotal role in this regard, particularly for hyperscaler and data center infrastructure customers. Alphawave Semi’s… Read More


Enabling Next Generation Silicon In Package Products

Enabling Next Generation Silicon In Package Products
by Kalar Rajendiran on 04-15-2021 at 10:00 am

System on Package Motivation AlphaWave IP

In early April, Gabriele Saucier kicked off Design & Reuse’s IPSoC Silicon Valley 2021 Conference. IPSoC conference as the name suggests is dedicated to semiconductor intellectual property (IP) and IP-based electronic systems. There were a number of excellent presentations at the conference. The presentations had been… Read More


Webinar Alert: High Bandwidth Memory ASIC SiPs for HPC and Networking Applications

Webinar Alert: High Bandwidth Memory ASIC SiPs for HPC and Networking Applications
by Mitch Heins on 08-22-2017 at 12:00 pm

Calling all ASIC designers working on High-Bandwidth Memory (HBM) access architectures in high-performance computing (HPC), networking, deep learning, virtual reality, gaming, cloud computing and data center applications. You won’t want to miss this upcoming webinar focused on system integration aspects of a HBM2 ASIC… Read More