WP_Term Object
    [term_id] => 4
    [name] => Open-Silicon
    [slug] => open-silicon
    [term_group] => 0
    [term_taxonomy_id] => 4
    [taxonomy] => category
    [description] => 
    [parent] => 386
    [count] => 41
    [filter] => raw
    [cat_ID] => 4
    [category_count] => 41
    [category_description] => 
    [cat_name] => Open-Silicon
    [category_nicename] => open-silicon
    [category_parent] => 386

Webinar Alert: High Bandwidth Memory ASIC SiPs for HPC and Networking Applications

Webinar Alert: High Bandwidth Memory ASIC SiPs for HPC and Networking Applications
by Mitch Heins on 08-22-2017 at 12:00 pm

 Calling all ASIC designers working on High-Bandwidth Memory (HBM) access architectures in high-performance computing (HPC), networking, deep learning, virtual reality, gaming, cloud computing and data center applications. You won’t want to miss this upcoming webinar focused on system integration aspects of a HBM2 ASIC SiP (Systems in Package). The HBM2 SiP is based on Open Silicon’s HBM2 IP-subsystem as implemented on TSMC’s 16nm FF+ process integrated with Samsung’s HBM2 memory using a TSMC CoWoS (chip-on-wafer-on-substrate) 2.5D silicon interposer.

HBM2, a 2016 JEDEC standard, offers wide-channel (128 bit) buses that can deliver up to 256 GBps bandwidth memory access. That’s screaming fast compared to the typical DDR3 access rates of 4GBps at one third the power efficiency. These architectures typically combine compute engine SoCs, with a 3D-stack of DRAM dice sometimes mounted on top a memory-controller ASIC. Stacked DRAM die interface using through-silicon-vias (TSVs) while the entire memory stack is then interfaced to the processing compute core using micro-bumps connections on short metal traces deposited on a thin, silicon-based interposer. System I/O make their way out of the package through a standard bump bonding on an organic package substrate (e.g. Chip-on-Wafer-on-Substrate).

 Open Silicon will be reviewing design aspects of their HBM2 IP-subsystem (memory controller, PHY and custom I/Os), including testability features for debug of the embedded chips in the SiP. Open Silicon will also be presenting validation data from a fabricated HBM2 SiP test platform design. Results will include data generated from four pseudo channels of the HBM2 memory using random, incremental, and walking 0’s and 1’s tests to mimic patterns typical of video buffer applications and network packet traffic. Silicon validation results will include calibration data on signal integrity and valid data window, power consumption of the HBM2 memory, HBM2 IP, ASIC core blocks and total power consumed by the 2.5D HBM2 ASIC SiP at various voltages and temperatures.

The seminar is hosted by Open Silicon and will be moderated by Herb Reiter, president of Eda-2-ASIC Consulting Inc. Herb has more than 20 years in technical and business roles at semiconductor and EDA companies and is currently driving the new System Scaling Working Group at the Electronic System Design Alliance (formerly known as EDAC).

 Presenting at the seminar will be Open Silicon’s Kalpesh Sanghvi and Vinay Somanache. Kalpesh has over a decade of professional experience in the semiconductor and embedded industry and is currently responsible for business development and technical pre-sales/support for Open Silicon’s IP.

Vinay has nearly two decades of experience in architecture and IP design engineering along with a wide variety of protocols and currently serves as Principal Architect of IP for Open Silicon.

Make sure to add this webinar to your calendar. It will be given on Tuesday, September 19, 2017 at 8:00AM PDT / 11:00AM EDT. Click this link to register now:

High Bandwidth Memory ASIC SiPs for High Performance Computing and Networking Applications

About Open-Silicon
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software and IP — and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 125 million ASICs to date. Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world. To learn more, visit www.open-silicon.com

Share this post via:


There are no comments yet.

You must register or log in to view/post comments.