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Multi-Channel Multi Rate FEC Engine Webinar with Open Silicon

Multi-Channel Multi Rate FEC Engine Webinar with Open Silicon
by Eric Esteve on 11-29-2017 at 12:00 pm

I will be pleased to moderate on December 7[SUP]th[/SUP] the Open-Silicon webinar addressing the benefits of the multi-channel multi-rate forward error correction (MCMR FEC) IP and the role it plays in high-bandwidth networking applications, especially those where the bit error rate is very high, such as high speed SerDes 30G and above.

Open Silicon’s multi channel, multi rate (MCMR) forward error correction (FEC) engine is fully configurable to support 400G/200G/100G/50G/25G rates on multiple channels. The panelist will outline use cases and discuss the key technical advantages that the MCMR FEC IP core offers, such as support for up to 56Gbps SerDes integration, bandwidth of up to 400G, support for KP4 RS (544,514) and KR4 RS (528,514), support for Interlaken, Flex Ethernet and 802.3x protocols, support for configurable alignment marker, and PRBS test pattern generator and loopback test.


If you are not familiar with Reed-Solomon codes, let’s take a quick look at the terminology. The NRZ and the PAM-4 PHY have most of their processing in common, but their biggest difference in the PHY architectures is that the NRZ PHY uses an RS(528,514, t=7, m=10) code with 10-bit symbols (m=10) that has an error-correction capability of t=7 (seven 10-bit symbols can be corrected), whereas the PAM-4 PHY uses an RS(544, 514, t=15, m=10) code with error-correction capability of t=15.

If you look at the above table, the PHY using NRZ signaling, 100GBASE-KR4, only support high quality PCB, when the PAM-4 PHY, 100GBASE-KP4, can support lower quality, standard PCB. When the medium quality is lower, you expect to correct more error, so the higher number (t=15) associated with RS(544,514) than for the NRZ PHY used on high quality PCB, where t=7, associated with RS(528,514).


The panelists will also discuss the architectural advantages of the core, such as its flexibility, configurability and scalability, all of which enable the MCMR FEC IP to be uniquely tailored to address customer specific application requirements. The MCMR FEC IP is part of Open-Silicon’s networking IP portfolio that includes the company’s Interlaken IP core, as well as its new Ethernet PCS and Flex Ethernet IPs, which enable high-bandwidth chip-to-chip, Ethernet endpoint and Ethernet transport applications.

The MCMR FEC IP features list:
Programmable common and unique alignment marker for each lane
Supports both KP4 (544, 514) and KR4 (528, 514) forward error correction and parity calculation. Supports both runtime and static configuration.
PRBS generator for test pattern generator
Support statistics reports, exception detection and error reporting
Runtime configurable FEC bypass operation
Supports lane re-ordering
Supports 50G and 25G SerDes rates
Supports 400G/200G/100G/50G/25G operation

This webinar is ideal for chip designers and SoC architects of high-speed, high-performance communication and computing applications such as packet processing/NPU, traffic management, switch fabric, switch fabric interface, Framer/Mapper, TCAMs, Serial Memory, FPGA and more.

For registration to this webinar, taking place on Thu, Dec 7, 2017 5:00 PM – 6:00 PM CET or 11:00 AM – 12:00 EST, please visit:

Open Silicon FEC Webinar

About Open-Silicon
Open-Silicon is a system-optimized ASIC solution provider that innovates at every stage of design to deliver fully tested IP, silicon and platforms. To learn more, please visit www.open-silicon.com.

By Eric Esteve from IPnest


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