The end-to-end principle as defined by Wikipedia is a design framework in computer networking. In networks designed according to this principle, application-specific features reside in the communicating end nodes of the network, rather than in intermediary nodes, such as gateways and routers, that exist to establish the network. There are usually tradeoffs between reliability, latency, and throughput. High-reliability networks usually negatively impact the other components of the parameters of this data transmission triad, namely latency and throughput. This is particularly important for applications that value predictable throughput and low latency over reliability – the classic example being interactive real-time voice applications.
Another example of end-to-end application is the network that handles on-demand content delivery from preparing, packaging the audio/video assets adding metadata, transcoding them and then sending them to distributors. It goes without saying that end-to-end networking solutions need to satisfactorily address these requirements for fast reliable transfer and delivery and it is thus not surprising to see that ASIC standardized solutions are best suited for the task. Those solutions are needed by leading-edge networking applications, such as long-haul, metro and core, broadband access, optical, carrier IP and data center interconnect use cases.
Open-Silicon, Credo, and IQ-Analog have put together a complete end-to-end ASIC solution for leading-edge networking applications, such as long-haul, metro, and core, broadband access, optical, carrier IP and data center interconnect which they have showcased at OFC 2018 last month.Open-Silicona comprehensive Networking IP Subsystem Solution, which includes high-speed chip-to-chip interface Interlaken IP, Ethernet Physical Coding Sublayer (PCS) IP, FlexE IP compliant to OIF Flex Ethernet standard v1.0 and will be compliant to the upcoming v2.0, and Multi-Channel Multi-Rate Forward Error Correction (MCMR FEC) IP. Open-Silicon complements this with its High Bandwidth Memory (HBM2) IP Subsystem Solution.
Credo has its high-speed 56Gbps PAM4 LR Multi-Rate SerDes solution and 112Gbps PAM4 SR/LR SerDes targeted for next-generation networking ASICs. IQ-Analog rounds up the solution with its high-performance, patented TPWQ hyper-speed 90Gsps ADC/DAC IPs analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). This teaming up gives the three companies the opportunity to demonstrate the power of complete solutions for the next generation of high-performance networking applications.
Open-Silicon has a comprehensive Networking IP Subsystem Solution portfolio and includes:
1.High Speed Chip-to-Chip Interface Interlaken IP – Open Silicon’s 8th generation Interlaken IP core supports up to 1.2 Tbps high-bandwidth performance and up to 56 Gbps SerDes rates with Forward Error Correction (FEC). This high-speed chip-to-chip interface IP features an architecture that is fully flexible, configurable and scalable, making it ideal for high-bandwidth networking applications, such as routers, switches, Framer/MAC, OTN switch, packet processors, traffic managers, look aside processors/memories, data center applications, and several other high-end networking and data processing applications.
2.Ethernet Physical Coding Sublayer (PCS) IP – Open-Silicon’s Ethernet PCS core is compatible with different MII interfaces for connecting to the MAC and is uniquely built to work with off-the-shelf MAC and SerDes from leading technology vendors. It supports 64b/66b encoding/decoding for transmit and receive, and various data rates, ranging from 10G to 400G. The Ethernet PCS IP complies with the IEEE 802.3 standard and supports Ethernet and Flex Ethernet interfaces, making it ideal for high-bandwidth Ethernet endpoint and Ethernet transport applications. https://www.open-silicon.com/networking-ip-subsystem/
3.Flex Ethernet (FlexE) IP – Open-Silicon’s FlexE IP core features a generic mechanism that supports various Ethernet MAC rates, and is uniquely built to work with Open-Silicon’s packet interface and OTN client interface or off-the-shelf MACs. The FlexE IP supports the Optical Internetworking Forum (OIF) Flex Ethernet standard 1.0 and will be compliant with the upcoming v2.0. The IP supports FlexE aware, FlexE unaware, and FlexE terminate modes of mapping over the transport network, making it ideal for high-bandwidth Ethernet transport applications. https://www.open-silicon.com/networking-ip-subsystem/
4.Forward Error Correction (FEC) IP – Open-Silicon’s FEC IP core is capable of multi-channel multi-rate forward error correction in applications where the bit error rate is very high, such as high-speed SerDes 30G and above, and significantly improves bandwidth by enabling 56G PAM4 SerDes integration. This single-instance IP core is compatible with off-the-shelf SerDes from leading technology vendors and supports bandwidths up to 400G with the ability to connect 32 SerDes lanes. It can easily achieve a Bit Error Rate (BER) of 10-6, which is required by most electrical interface standards using PAM4 SerDes. The FEC IP core supports the Interlaken and Ethernet standards and significantly improves bandwidth by enabling high speed, multi-channel SerDes integration, making it ideal for high-bandwidth networking applications. https://www.open-silicon.com/networking-ip-subsystem/
5.High Bandwidth Memory (HBM2) IP Subsystem Solution – Comprehensive High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASICs in FinFET Technologies – This solution is now available for 2.5D ASIC design starts and also as licensable Intellectual Property (IP). The IP includes the controller, PHY and custom die-to-die I/O needed to drive the interface between the logic-die and the memory die-stack on the 2.5D interposer. Open-Silicon’s HBM2 IP subsystem is silicon proven on a 2.5D HBM2 ASIC SiP (System-in-Package) platform. The platform is used to demonstrate the high bandwidth data transfer rates of >2Gbps and interoperability between Open-Silicon’s HBM2 IP subsystem and HBM2 memory die-stack. http://www.open-silicon.com/high-bandwidth-memory-ip/
Open-SiliconNetworking IP Subsystem Solution
- High-speed chip-to-chip interface Interlaken IP
- Ethernet Physical Coding Sublayer (PCS) IP
- FlexE IP compliant to OIF Flex Ethernet standard v1.0 and will be compliant with the upcoming v2.0
- Multi-Channel Multi-Rate Forward Error Correction (MCMR FEC) IP
- High Bandwidth Memory (HBM2) IP Subsystem Solution
- High-speed 56Gbps PAM4 LR Multi-Rate SerDes solution
- 112Gbps PAM4 SR/LR SerDes targeted for next-generation networking ASICs
- High-performance analog-to-digital converters (ADCs)
- High-performance digital-to-analog converters (DACs).