AI is revolutionizing and transforming virtually every industry in the digital world. Advances in computing power and deep learning have enabled AI to reach a tipping point toward major disruption and rapid advancement. However, these applications require much higher performance and bandwidth requiring new kinds of IP and that brings us to Open-Silicon and the Interlaken IP.
Open-Silicon, a founding member of the Interlaken Alliance formed in 2007, launched the 8[SUP]th[/SUP]generation of Interlaken IP core supporting up to 1.2 Tbps bandwidth last year. This high-speed chip-to-chip interface IP features an architecture that is fully flexible, configurable and scalable.
The Interlaken IP subsystem originally developed for networking applications is enabling high speed chip to chip interface for deep learning SoCs. Open-Silicon’s eighth-generation Interlaken IP supports up to 1.2Tbps high-bandwidth performance and up to 56 Gbps SerDes rates with Forward Error Correction (FEC). Interlaken IP is a scalable, high-speed chip-to-chip interface protocol that builds on the channelization and per-channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology, similar to XAUI. Open-Silicon’s ILKN FEC IP core meet the requirements Interlaken protocol to significantly improve bandwidth by enabling high speed SerDes integration. The FEC can easily achieve a BER (Bit Error Rate) of 10-15, which is required by most electrical interface standards using high speed SerDes built upon a flexible and robust architecture.
The updated Interlaken specification is capable of supporting SerDes beyond 30Gbps and up to 58Gbps—this was mainly because of the introduction of the peer-to-peer service, which allows sending more data on fewer lines. This led to development of Open-Silicon’s eighth generation Interlaken IP core, supporting up to 1.2 Tbps high performance and up to 56 Gbps SerDes rates with Forward Error Correction (FEC) https://www.open-silicon.com/open-silicon-ips/interlaken-controller-ip/
- Fully-programmable SerDes lane mapping
- Interlaken-LA 4-channel protocol
- Up to 56 Gbps SerDes support
- 1.2 Tbps high-bandwidth performance
- Interlaken Retransmit Extension support
In addition to the key features highlighted with the latest release, the Open-Silicon Interlaken IP also provides the following feature set as part of the standard IP functionality:
- Support for 256 logical channels
- 8-bit channel extension for up to 64K channels
- Independent SerDes lane enable/disable
- Support for SerDes speeds from 3.125Gbps to 56 Gbps
- Configurable number of lanes from 1 to 48
- Flexible user interface options:
- 128b: 1x128b, 2x128b, 4x128b, or 8x128b
- 256b: 1x256b, 2x256b, 4×256, or 8x256b
- Programmable BURSTMAX from 64 bytes – 512 bytes
- Programmable BURSTMIN from 32 bytes – 256 bytes
- Simultaneous In-band and Out-of-Band flow control
- Programmable calendar
- Built-in error detection and interrupt structures
- Configurable error injection mechanisms for test-ability
“Open-Silicon’s Interlaken IP Subsystem delivers the bandwidth scalability and performance we require for various artificial intelligence applications that require high speed inter-node connectivity. The Interlaken IP subsystem is extremely configurable and robust, which enables the high-bandwidth efficiencies required for deep learning SoCs.”-Open-Silicon Customer
Since 2007 Open-Silicon’s Interlaken IP has been deployed in several different tier-1 networking and computing customer products. Many of these products are shipping in production today in the latest technology nodes in multiple foundries. The unique flexibility and configurability built into Open-Silicon’s Interlaken core meets not only today’s technological requirements, but remains fully compatible with older designs.
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Open-Silicon is a system-optimized ASIC solution provider that innovates at every stage of design to deliver fully tested IP, silicon and platforms. To learn more, please visit www.open-silicon.com