If you are interested in what types of chips we will see in the coming years always ask an ASIC provider because they know. Companies of all sizes (small-medium-large) use ASIC companies to get their chips out in the least amount of time and at a minimum cost because that is what ASIC companies do.
IP is an important ingredient to the ASIC business model of course and it is easy to see the types of IP that are attracting the big ASIC customers, all you have to do is look at the ASIC company press releases and webinars:
Comprehensive IP subsystem includes Interlaken, Ethernet PCS, Flex Ethernet and Forward Error Correction IPs
“More and more enterprises and small/medium businesses are shifting their IT investments from in-house IT infrastructure to cloud-based IT services—spending on cloud services is on track to rise by over 30% in 2017,” said Matthias Machowinski, Senior Research Director at IHS Markit. “In response, cloud service providers (CSPs) are heavily investing in their infrastructure, and are currently upgrading their networks to 25/100G. In anticipation of continuing growth, CSPs are already looking towards the future, and once 400G becomes available in 2018/2019, we expect them to rapidly adopt this new technology.”
Open-Silicon Unveils Industry’s Highest Performance Interlaken Chip-to-Chip Interface IP
Supports up to 1.2 Tbps and up to 56Gbps SerDes rates
“The 3rd-party IP ecosystem has always played a key role in the industry. And now, with the unstoppable growth of high-bandwidth networking applications together with the desire to further technological advancements on a much quicker cadence, the demand for industry consortium standards that ensure interoperability grows sharply,” stated Michael Howard, senior research director and advisor, carrier networks at IHS Markit. “It is for these reasons that solutions such as this chip-to-chip Interlaken IP core, will likely have high adoption into next-generation routers and switches, packet processors, and high-end networking and data processing applications.”
Open-Silicon Completes Successful Silicon Validation of High Bandwidth Memory (HBM2) IP Subsystem Solution
Silicon validation in TSMC’s 16nm FinFET technology and interoperability with HBM2 memory; Silicon-proven SoC solution enables next generation high bandwidth applications
“Open-Silicon’s successful silicon validation of an HBM2 IP subsystem in 16nm means that volume production of HBM2 ASIC SiPs are now a reality,” said Herb Reiter, President, eda2asic Consulting, Inc. and author of the most recent Multi-Die IC User Guide, co-sponsored by the Electronic System Design Alliance (ESD Alliance). “The benefit to the industry is significant, in that system developers of high bandwidth applications can minimize risk and time-to-market by having access to a complete silicon-proven HBM IP subsystem, and design/manufacturing of HBM2 ASIC SiPs from a single vendor.”
Open-Silicon Receives TSMC OIP Ecosystem Forum Customers’ Choice Award for Best Paper
High Bandwidth Memory (HBM2) IP Subsystem Solution Validation and Interoperability with HBM2 Memory Die Stack
“TSMC has a very selective process for accepting papers, and those that are chosen represent the highest quality and highest value to our customers,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “Receiving the Customers’ Choice Award for the best paper clearly demonstrates the high level of interest in Open-Silicon’s HBM2 IP subsystem solution and the benefits it offers to our mutual customers using TSMC FinFET and CoWoS® technologies.”
One of the trends I have been tracking on SemiWiki is systems companies using ASIC services rather than investing millions of dollars in hiring or acquiring a team and tools. From the SemiWiki analytics you can see an increasing amount of non-traditional chip companies researching IP, EDA tools, foundry and ASIC services. It really is encouraging to see the systems companies investing in the fabless semiconductor ecosystem making the ASIC business great again, absolutely.