Chip-on-Wafer-on-Substrate, commonly called CoWoS, is an advanced packaging platform developed by TSMC. It allows processors, chiplets, and high-bandwidth memory stacks to be integrated within a single package. CoWoS has become especially important for artificial-intelligence accelerators and high-performance computing… Read More
Advanced semiconductor packaging has become essential to improving computing performance as conventional transistor scaling grows more difficult and expensive. Instead of manufacturing an entire processor as one large monolithic die, chipmakers can divide it into smaller chiplets and combine logic, memory, input/output… Read More
There has been talk at the latest conferences about TSMC customers taking wafers to Intel for packaging. The question is why? Is it competitive pricing? Capacity? Supply chain diversity? CC Wei was asked about this during the last investor call and his perfect response was:
Jeff Su: I guess very simply put, EMIB-T, in his view, is… Read More
The worldwide TSMC 2025 Technology Symposium recently kicked off with the first event in Santa Clara, California. These events typically focus on TSMC’s process technology and vast ecosystem. These items were certainly a focus for this year’s event as well. But there is now an additional item that shares the spotlight – packaging… Read More
At the 2024 TSMC OIP Ecosystem Forum, one of the technical talks by TSMC focused on maximizing 3DIC design productivity and rightfully so. With rapid advancements in semiconductor technology, 3DICs have become the next frontier in improving chip performance, energy efficiency, and density. TSMC’s focus on streamlining the… Read More
Recently, TSMC held their 26th annual Technology Symposium, which was conducted virtually for the first time. This article is the second of three that attempts to summarize the highlights of the presentations. This article focuses on the TSMC advanced packaging technology roadmap, as described by Doug Yu, VP, R&D.
Key… Read More
