Tag: packaging

Webinar: Enhanced Packaging Performance and Manufacturing with Physics-Based 3D Simulation

Webinar: Enhanced Packaging Performance and Manufacturing with Physics-Based 3D Simulation
by Admin on 08-20-2024 at 8:51 pm

Join this webinar for the latest updates on virtual engineering simulation capabilities in the primary and secondary packaging domain. Showcasing physics-based 3D simulation for performance insight during storage, transportation, and manufacture.

Date:
Thursday, September 5, 2024

Time:
15:00 BST, 16:00 CEST, 10:00 EDT

… Read More

Packaging Failure and Yield Analysis

Packaging Failure and Yield Analysis
by Admin on 07-24-2024 at 2:50 pm

Failure and Yield Analysis is an increasingly difficult and complex process. Today, engineers are required to locate defects on complex integrated circuits. In many ways, this is akin to locating a needle in a haystack, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand… Read More

Packaging Failure and Yield Analysis

Packaging Failure and Yield Analysis
by Admin on 07-23-2024 at 7:01 pm

Failure and Yield Analysis is an increasingly difficult and complex process. Today, engineers are required to locate defects on complex integrated circuits. In many ways, this is akin to locating a needle in a haystack, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand… Read More

Webinar: Reducing Semiconductor Packaging Defects with Ansys Tools

Webinar: Reducing Semiconductor Packaging Defects with Ansys Tools
by Admin on 04-12-2024 at 2:07 pm

Ansys Semiconductor Manufacturing Webinar Series: Part 2 of 3.

Join us on Thursday, May 23rd for an in-depth discussion on reducing defects in the semiconductor packaging process.

Learn more about the webinar series!

TIME:
THURSDAY, MAY 23, 2024
11 AM EASTERN TIME

Venue:
Virtual

Overview

Semiconductor packaging involves integrating

… Read More

GSA 2024 European Executive Forum

GSA 2024 European Executive Forum
by Admin on 03-15-2024 at 2:06 pm

The GSA European Executive Forum is our flagship event in Europe which, over two days, always attracts the very top speakers and attendees: 300 senior decision makers, the majority VP and C-level profiles.

Over the past 20 years, it has become the reference executive event for the semiconductor industry in the EMEA region.

This… Read More

Posted on

IEDM 2022 – Ann Kelleher of Intel – Plenary Talk

IEDM 2022 – Ann Kelleher of Intel – Plenary Talk
by Scotten Jones on 12-06-2022 at 10:00 am
Categories: Events, Foundries, Intel, Semiconductor Services, TechInsights
7 Comments

Ann 2022 IEDM Plenary Dec. 5 Roadmap Slide

Ann Kelleher is Intel’s Executive Vice President, General Manager, Technology Development, and she gave the first plenary talk to kick off the 2022 IEDM, “Celebrating 75 Years of the Transistor A Look at the Evolution of Moore’s Law Innovation”. I am generally not a fan of plenary talks because I think they are often too broad and… Read More

Posted on

Mentor unpacks LVS and LVL issues around advanced packaging

Mentor unpacks LVS and LVL issues around advanced packaging
by Tom Simon on 11-26-2019 at 6:00 am
Categories: EDA, Siemens EDA

Innovations in packaging have played an important role in improving system performance and area utilization. Advances like 2.5D interposers and fan-out wafer-level packaging (FOWLP) have allowed mixed dies to be used in a single package and have dramatically reduced the number of connections that need to go all the way to the… Read More

Posted on

Design for Fanout Packaging

Design for Fanout Packaging
by Bernard Murphy on 12-12-2016 at 12:00 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

In constant pursuit of improved performance, power and cost, chip and system designers always want to integrate more functions together because this minimizes inter-device loads (affecting performance and power) and bill of materials on the board (affecting cost). However it generally isn’t possible to integrate … Read More

Posted on

3DIC in Burlingame

3DIC in Burlingame
by Paul McLellan on 12-01-2014 at 7:00 am
Categories: Events

Every year in December is what I think of as the main 3D IC conference where you can get up to speed on all the latest. Officially it is called 3D Architectures for Semiconductor and Packaging or 3D ASIP. It is held in the Hyatt Regency in Burlingame (the one right by 101 near the airport). This year it is from December 10-12th.

The first… Read More

Posted on

3DIC, the World Goes to…Burlingame

3DIC, the World Goes to…Burlingame
by Paul McLellan on 10-23-2013 at 2:09 pm
Categories: Uncategorized

For the tenth year, the big 3DIC conference takes place in the Hyatt Regency at Burlingame (just south of San Francisco Airport). Officially it is 3D Architectures for Semiconductor Integration and Packaging or ASIP. This year there have already been some significant 3D announcements: TSMC’s 3D program, and Micron’s… Read More