Solving the EDA tool fragmentation crisis

Solving the EDA tool fragmentation crisis
by Admin on 04-30-2026 at 10:00 am

fig1 cci flow (1)

By Samar Abd El-Hady and Wael ElManhawy

Design teams today face an uncomfortable truth: the specialized tools they need to verify modern ICs can’t reliably share the same design data. As geometries shrink below five nanometers and designs incorporate billions of transistors across multiple dies, no single Electronic… Read More


Closing the Reality Gap: A New Architecture for 1.8-Tb/s Chiplet Governance

Closing the Reality Gap: A New Architecture for 1.8-Tb/s Chiplet Governance
by Admin on 04-26-2026 at 4:00 pm

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By Dr. Moh Kolbehdari

Dr. Moh Kolbehdari is a Senior Lead Architect at Socionext, where he specializes in the industrialization of high-performance AI chiplets and 1.8-Tb/s interconnects. With over two decades of experience in SI/PI, electromagnetic field theory, and system-level architecture, he has been a pivotal force… Read More


Carbon in the Age of AI Chips: What the Semiconductor Industry Needs to Know This Earth Day

Carbon in the Age of AI Chips: What the Semiconductor Industry Needs to Know This Earth Day
by Admin on 04-23-2026 at 6:00 am

Carbon in the Age of AI Chips

Stephen Russell: Senior Technical Fellow, TechInsights

Every April, Earth Day prompts a flurry of corporate sustainability pledges and green-tinted press releases. But for the semiconductor industry in 2026, the conversation has moved well past pledges. Carbon accountability is now a procurement requirement, a regulatory… Read More


Speculation: Silicon’s Most Expensive Compulsion

Speculation: Silicon’s Most Expensive Compulsion
by Admin on 04-16-2026 at 10:00 am

SemiWiki Art

How Time-Based Scheduling
Reclaims Silicon Wasted by Speculative Execution

By: Dr. Thang Tran, Founder and CTO, Simplex Micro

I have spent my career designing processor architectures, and I have reached an uncomfortable conclusion: a substantial fraction of the silicon area and power in modern high-performance processors… Read More


When a Platform Provider Becomes a Competitor: Why Arm’s Silicon Strategy Changes the Incentives

When a Platform Provider Becomes a Competitor: Why Arm’s Silicon Strategy Changes the Incentives
by Admin on 04-12-2026 at 12:00 pm

RISC V Now Andes Conference

Marc Evans, Director of Business Development & Marketing, Andes Technology USA

I work at a RISC-V IP company, and I genuinely root for Arm — probably more than most people in my position would admit. Not because I’m confused about who competes with whom, but because Arm’s best move for their shareholders is also… Read More


When a Platform Provider Becomes a Competitor: Why Arm’s Silicon Strategy Changes the Incentives

When a Platform Provider Becomes a Competitor: Why Arm’s Silicon Strategy Changes the Incentives
by Admin on 04-07-2026 at 10:00 am

SemiWiki

Marc Evans, Director of Business Development & Marketing, Andes Technology USA

I work at a RISC-V IP company, and I genuinely root for Arm — probably more than most people in my position would admit. Not because I’m confused about who competes with whom, but because Arm’s best move for their shareholders is also… Read More


Why Your LLM-Generated Testbench Compiles But Doesn’t Verify: The Verification Gap Problem

Why Your LLM-Generated Testbench Compiles But Doesn’t Verify: The Verification Gap Problem
by Admin on 03-10-2026 at 10:00 am

fig1 vg chart

By Vikash Kumar, Senior Verification Architect | Arm | IEEE Senior Member. 

The Problem Every Verification Engineer Recognizes

You ask an LLM to generate a UVM testbench. It produces 25 files. Everything compiles. You run the simulation — and nothing happens. The scoreboard reports zero checks. The slave driver stops after 10… Read More


Securing RISC-V Third-Party IP: Enabling Comprehensive CWE-Based Assurance Across the Design Supply Chain

Securing RISC-V Third-Party IP: Enabling Comprehensive CWE-Based Assurance Across the Design Supply Chain
by Admin on 03-02-2026 at 10:00 am

RISC V 3PIP CWE Workflow BR 022626

by Jagadish Nayak

RISC-V adoption continues to accelerate across commercial and government microelectronics programs. Whether open-source or commercially licensed, most RISC-V processor cores are integrated as third-party IP (3PIP), potentially introducing supply chain security challenges that demand structured,… Read More


How Switzerland Built a Global Semiconductor Edge by Thinking Smaller

How Switzerland Built a Global Semiconductor Edge by Thinking Smaller
by Admin on 02-03-2026 at 8:00 am

Alain Serge Porret Headshot

By Alain-Serge Porret, Vice President, Integrated & Wireless Systems, CSEM

Since ramping up several years ago, the global semiconductor and artificial intelligence (AI) race has been driven by scale, from building larger data centers, developing bigger and more powerful models, and with them, increasingly complex and… Read More


Last Call: Why Your Real‑World Lessons Belong in DAC 2026’s Engineering

Last Call: Why Your Real‑World Lessons Belong in DAC 2026’s Engineering
by Admin on 01-15-2026 at 6:00 am

DAC Call for Contributions 2026

By Frank Schirrmeister, Synopsys
Disclaimer: This article is written in my role as Engineering Track Chair for DAC 2026

If you’ve ever walked out of DAC with a handful of practical ideas you could put to work when you return to work, you already know the value of the Engineering Track. It’s where practitioners talk to practitioners… Read More