How early symmetry validation eliminates costly late-stage respins

How early symmetry validation eliminates costly late-stage respins
by Admin on 07-27-2026 at 2:00 pm

article fig1 shift left

By Mauli Shah, Product Engineer, Siemens

Analog and mixed-signal design teams face a persistent challenge that directly impacts tape-out schedules and project predictability: symmetry violations discovered at signoff trigger expensive respins, delay schedules and create unpredictable iteration cycles. Despite symmetry… Read More


Rethinking Formal Verification in the AI Era

Rethinking Formal Verification in the AI Era
by Admin on 07-27-2026 at 10:00 am

AI driven formal verification

By Kanav Arora, ML Researcher at ChipAgents

Most hardware teams already understand why formal verification matters. It can expose corner cases that simulation may never reach and establish critical behaviors across the modeled state space.

The unresolved question is not whether formal works. It is why formal remains a specialist… Read More


How Fast Can a Performance Model Actually Be Built?

How Fast Can a Performance Model Actually Be Built?
by Admin on 07-26-2026 at 4:00 pm

SimplEx MicroCircuitSutra Performance Model 2026 07 20 Fig

By Thang Tran, CEO of Simplex Micro and Umesh Sisodia, CEO of CircuitSutra

Performance models have a reputation problem. They’re often treated as a long-lead, high-effort undertaking — something a design team commits to early and then waits on for months before it’s useful. The development of SimplEx Micro’s… Read More


Enhancing Multi-Domain System Simulation with FMI Co-Simulation

Enhancing Multi-Domain System Simulation with FMI Co-Simulation
by Admin on 06-30-2026 at 2:00 pm

fig01 Stepper AMS

As systems become increasingly complex across every field of science and engineering, the importance of computer simulation in design, analysis, and verification continues to increase over time. The traditional process in which a system is modeled and simulated in a single tool is called monolithic simulation. On the other… Read More


GPU-native mask rule checking eliminates the curvilinear mask rule check bottleneck

GPU-native mask rule checking eliminates the curvilinear mask rule check bottleneck
by Admin on 06-16-2026 at 10:00 am

fig1 gpu opc challenge

As semiconductor manufacturing pushes toward advanced nodes with tighter feature sizes, the optical proximity correction (OPC) workflow is adopting curvilinear masks to achieve the larger process windows that traditional Manhattan geometries cannot deliver.

Traditional Manhattan masks constrain shapes to vertical … Read More


John Barr: The EDA Veteran and Award-Winning Needham Funds Portfolio Manager

John Barr: The EDA Veteran and Award-Winning Needham Funds Portfolio Manager
by Admin on 05-31-2026 at 4:00 pm

John Barr Needham & Company

John Barr, Portfolio Manager of the top-ranked Needham Aggressive Growth Fund, has built a career with skills honed not just on Wall Street, but in the trenches of the early EDA industry.

Before becoming a respected sell-side analyst and later a buy-side portfolio manager, Barr spent 15 years in the EDA industry, working through… Read More


SoC PLANNER: A New Generation of SoC Design Exploration Solution Managing Cost-effectiveness and Sustainability

SoC PLANNER: A New Generation of SoC Design Exploration Solution Managing Cost-effectiveness and Sustainability
by Admin on 05-27-2026 at 10:00 am

Defacto SoC Planner

With over a trillion chips manufactured every year and application requirements evolving faster than ever (across automotive, HPC, and AI), the pressure on SoC design teams has never been higher with design space keeps growing and schedules keep shrinking.

Indeed, for a complex SoC project, the number of possible configurations… Read More


Crossing the Yield Cliff: IDP V6 and the Future of Manufacturing Forecasting

Crossing the Yield Cliff: IDP V6 and the Future of Manufacturing Forecasting
by Admin on 05-18-2026 at 10:00 am

Crossing the Yield Cliff IDP V6 and the Future of Manufacturing Forecasting

The paper, Industrial Defectivity Prediction (IDP) V6: A Two-Layer Yield Cliff Framework for Cross-Industry Mass-Production Forecasting, presents a generalized industrial yield-modeling architecture that extends the classical Negative Binomial framework through a two-layer phenomenological structure designed … Read More


Solving the EDA tool fragmentation crisis

Solving the EDA tool fragmentation crisis
by Admin on 04-30-2026 at 10:00 am

fig1 cci flow (1)

By Samar Abd El-Hady and Wael ElManhawy

Design teams today face an uncomfortable truth: the specialized tools they need to verify modern ICs can’t reliably share the same design data. As geometries shrink below five nanometers and designs incorporate billions of transistors across multiple dies, no single Electronic… Read More


Carbon in the Age of AI Chips: What the Semiconductor Industry Needs to Know This Earth Day

Carbon in the Age of AI Chips: What the Semiconductor Industry Needs to Know This Earth Day
by Admin on 04-23-2026 at 6:00 am

Carbon in the Age of AI Chips

Stephen Russell: Senior Technical Fellow, TechInsights

Every April, Earth Day prompts a flurry of corporate sustainability pledges and green-tinted press releases. But for the semiconductor industry in 2026, the conversation has moved well past pledges. Carbon accountability is now a procurement requirement, a regulatory… Read More