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John Barr, Portfolio Manager of the top-ranked Needham Aggressive Growth Fund, has built a career with skills honed not just on Wall Street, but in the trenches of the early EDA industry.
Before becoming a respected sell-side analyst and later a buy-side portfolio manager, Barr spent 15 years in the EDA industry, working through… Read More
With over a trillion chips manufactured every year and application requirements evolving faster than ever (across automotive, HPC, and AI), the pressure on SoC design teams has never been higher with design space keeps growing and schedules keep shrinking.
Indeed, for a complex SoC project, the number of possible configurations… Read More
The paper, Industrial Defectivity Prediction (IDP) V6: A Two-Layer Yield Cliff Framework for Cross-Industry Mass-Production Forecasting, presents a generalized industrial yield-modeling architecture that extends the classical Negative Binomial framework through a two-layer phenomenological structure designed … Read More
By Samar Abd El-Hady and Wael ElManhawy
Design teams today face an uncomfortable truth: the specialized tools they need to verify modern ICs can’t reliably share the same design data. As geometries shrink below five nanometers and designs incorporate billions of transistors across multiple dies, no single Electronic… Read More
Stephen Russell: Senior Technical Fellow, TechInsights
Every April, Earth Day prompts a flurry of corporate sustainability pledges and green-tinted press releases. But for the semiconductor industry in 2026, the conversation has moved well past pledges. Carbon accountability is now a procurement requirement, a regulatory… Read More
How Time-Based Scheduling
Reclaims Silicon Wasted by Speculative Execution
By: Dr. Thang Tran, Founder and CTO, Simplex Micro
I have spent my career designing processor architectures, and I have reached an uncomfortable conclusion: a substantial fraction of the silicon area and power in modern high-performance processors… Read More
Marc Evans, Director of Business Development & Marketing, Andes Technology USA
I work at a RISC-V IP company, and I genuinely root for Arm — probably more than most people in my position would admit. Not because I’m confused about who competes with whom, but because Arm’s best move for their shareholders is also… Read More
Marc Evans, Director of Business Development & Marketing, Andes Technology USA
I work at a RISC-V IP company, and I genuinely root for Arm — probably more than most people in my position would admit. Not because I’m confused about who competes with whom, but because Arm’s best move for their shareholders is also… Read More
By Vikash Kumar, Senior Verification Architect | Arm | IEEE Senior Member.
The Problem Every Verification Engineer Recognizes
You ask an LLM to generate a UVM testbench. It produces 25 files. Everything compiles. You run the simulation — and nothing happens. The scoreboard reports zero checks. The slave driver stops after 10… Read More
RISC-V adoption continues to accelerate across commercial and government microelectronics programs. Whether open-source or commercially licensed, most RISC-V processor cores are integrated as third-party IP (3PIP), potentially introducing supply chain security challenges that demand structured,… Read More
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ASML High-NA EUV is Not Ready for High-Volume Production