Hardwear.io Security Trainings and Conference NL 2026

Hardwear.io Security Trainings and Conference NL 2026
by Admin on 09-03-2026 at 1:13 am

Hardwear.io Netherlands 2026, expected in November, is one event you shouldn’t miss if hardware security is your thing. It’s where researchers, engineers, and hackers come together to take devices apart, dig into firmware, test real-world attack paths, and swap ideas with people who truly get the work.

With hands-on trainings,… Read More


Latest Savage on Security Webinar Focuses on Gen-AI for Chip Design and Security

Latest Savage on Security Webinar Focuses on Gen-AI for Chip Design and Security
by Admin on 08-19-2026 at 10:00 am

Savage on Security 3 SemiWiki 400 (1)


Key Takeaways from the webinar:
Multi-agent intelligent assistant systems of the future will be architected to automate and augment SoC design and security verification and redefining semiconductor innovation, reshaping design, verification and security for the next generation of trusted silicon.

The ESD Alliance is delighted… Read More


ESD Alliance Webinar: Gen-AI for Chip Design and Security

ESD Alliance Webinar: Gen-AI for Chip Design and Security
by Admin on 08-03-2026 at 7:27 pm

This webinar will present a multi-agent intelligent assistant system architected to automate and augment SoC design and security verification.

Designing functionally correct, high-performance, and provably secure system-on-chips (SoCs) has become a strategic imperative for modern computing infrastructure. Yet traditional… Read More


2026 Outlook with Krishna Anne of Agile Analog

2026 Outlook with Krishna Anne of Agile Analog
by Daniel Nenni on 01-22-2026 at 10:00 am

Agile Analog Krishna Anne headshot photo (1)

Tell us a little bit about yourself and your company.

I have worked in the global semiconductor industry for over 30 years, with major semiconductor companies such as Rambus, AMD and Broadcom, as well as with start-ups such as SCI Semiconductor and DataTrails. I started my career as a digital circuit designer, then moved into marketing,… Read More


A Six-Minute Journey to Secure Chip Design with Caspia

A Six-Minute Journey to Secure Chip Design with Caspia
by Mike Gianfagna on 11-11-2025 at 6:00 am

A Six Minute Journey to Secure Hardware Design with Caspia

Hardware-level chip security has become an important topic across the semiconductor ecosystem. Thanks to sophisticated AI-fueled attacks, the hardware root of trust and its firmware are now vulnerable. And unlike software security, an instantiated weakness cannot be patched. The implications of such vulnerabilities are… Read More


Think Quantum Computing is Hype? Mastercard Begs to Disagree

Think Quantum Computing is Hype? Mastercard Begs to Disagree
by Bernard Murphy on 11-10-2025 at 6:00 am

Just got an opportunity to write a blog on PQShield, and I’m delighted for several reasons. Happy to work with a company based in Oxford and happy to work on a quantum computing-related topic, which you’ll find I will be getting into more deeply over coming months. (Need a little relief from a constant stream of AI topics.) Also important,… Read More


Moores Lab(AI): Agentic AI and the New Era of Semiconductor Design

Moores Lab(AI): Agentic AI and the New Era of Semiconductor Design
by Kalar Rajendiran on 10-08-2025 at 10:00 am

Silicon Engineering at the Speed of AI

For decades, chip design has been a delicate balance of creativity and drudgery. Architects craft detailed specifications, engineers read those documents line by line, and teams write and debug thousands of lines of Verilog and UVM code. Verification alone can consume up to 35 percent of a project’s cost and add many months to … Read More


Prompt Engineering for Security: Innovation in Verification

Prompt Engineering for Security: Innovation in Verification
by Bernard Murphy on 07-30-2025 at 6:00 am

Innovation New

We have a shortage of reference designs to test detection of security vulnerabilities. An LLM-based method demonstrates how to fix that problem with structured prompt engineering. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford,… Read More