Analog Bits Targets the Power Challenge at the Heart of Next-Generation Chips

Analog Bits is expanding its role in advanced semiconductor design with new intellectual property aimed at one of the industry’s most difficult problems: delivering, monitoring, and managing power inside increasingly complex chips.

The company announced that its IP will be included in an upcoming customer test-chip tapeout using TSMC’s A14 process. It will also showcase real-time power-observability and sensing technology developed for TSMC’s N2P process at the 2026 TSMC Open Innovation Platform Ecosystem Forum. Through presentations with Cerebras, Arm, and Socionext, Analog Bits plans to demonstrate how smarter power delivery can support scalable systems-on-chip for artificial intelligence, data centers, automotive applications, and other demanding markets.

The A14 test chip is intended to help make Analog Bits’ next-generation IP silicon-proven, reducing the integration risk for customers adopting an advanced manufacturing process. At N2P, the company will demonstrate integrated on-die low-dropout regulators with glitch-catching and voltage-droop detection, pinless process-voltage-temperature sensors, and low-power phase-locked loops. Its remote pinless PVT sensors offer untrimmed temperature accuracy of plus or minus 3.5 degrees Celsius, while its PLLs operate at microwatt-class power levels.

These technologies provide chips with something increasingly valuable: an immediate view of their own operating conditions. Sensors can reveal changes in temperature, supply voltage, and manufacturing-related performance, while integrated regulators and clocking technologies can help the chip respond. That feedback can enable designers to optimize performance and energy consumption at a much finer level than system-wide controls permit.

Analog Bits will outline the broader technical case through three partner presentations. A paper co-authored with Cerebras, “On-Die Power Management for Scalable SoCs and Chiplet Architectures,” will address power integrity, efficiency, and reliability in AI and high-performance computing systems. A Socionext paper will discuss pinless PLL and PVT-sensor IP for data-center and automotive SoCs, emphasizing the elimination of dedicated analog power supplies. A third paper, co-authored with Arm, will explore integrated power and clock management for real-time, core-level optimization in N3P and N2P data-center processors.

Why It Matters

Power has become a fundamental constraint on computing progress. AI infrastructure may operate at the megawatt scale, while the individual SoCs powering it can consume several kilowatts. At the same time, transistor performance continues to increase without a proportional reduction in operating voltage. The result is greater power density, more heat, and tighter limits on how much performance designers can safely extract from advanced silicon.

Real-time, on-die observability helps address that problem at its source. Instead of relying only on measurements taken at the board or package level, designers can monitor conditions close to individual cores and functional blocks. When paired with integrated regulation and clock control, this information can support rapid adjustments to workloads, voltage, and frequency. Such localized control can improve energy efficiency while reducing the risk of voltage droops, timing failures, overheating, and premature device degradation.

The pinless design approach is also significant. Conventional analog functions may require dedicated supply pins and supporting circuitry, complicating chip packages and board designs. Eliminating some of those requirements can reduce cost, simplify integration, and make the same IP easier to scale across large SoCs and chiplet-based architectures.

Bottom line:  Participation in an A14 tapeout signals preparation for the generation beyond today’s leading production nodes. Customers generally want proof that critical IP works in actual silicon before committing it to expensive products. Analog Bits says billions of its IP cores have already been fabricated across processes ranging from 0.35 micron to 2 nanometers. Extending that record to A14, while demonstrating complementary technology at N2P, could position the company as an important supplier for future AI accelerators, hyperscale processors, automotive SoCs, and other systems in which power efficiency and reliability are inseparable from performance.

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Analog Bits Demos Real-Time On-Chip Power Sensing and Delivery on N2P at the TSMC 2026 Technology Symposium