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Cadence Mixed Signal Technology Summit

Cadence Mixed Signal Technology Summit
by Paul McLellan on 09-21-2012 at 6:46 pm

 Yesterday I attended some of the Cadence mixed-signal technology summit. The day ended with a panel session on Are We Closing the Gap Yet in Mixed-signal Design? Richard Goering moderated. The panelists were all mixed signal experts:

  • Nayaz Khan of Maxim
  • Nishant Shah of Broadcom
  • Shiv Sikand of IC Manage
  • Bill Meier of Texas Instruments
  • Bob Chizmadia of Cadence

The panelists were invited to say which gaps have been closed and where the current gaps are. There seems to be a large amount of agreement, in fact, in both the panel session and some of the sessions earlier in the day.

Problem #1: Adding analog into the digital flow is a sort of second class citizen, especially when trying to use SystemVerilog. Especially Connect Modules. And never mind multi-language.

Problem #2: People need to know a lot. Finding individuals who can work with object-oriented code and understand analog and understand power is really hard. As a result, AMS designs require an extra level of support. TI even have a program called AMSmadeEZ the Bill heads up. Ideally you want a separate team for AMS verification since it is much more effective if people do it a lot and not just a couple of times per year. TI and Maxim seemed to do this.

Problem #3: It is really hard to keep all the files aligned between the analog world and the digital world. Especially keeping the models the digital people need of the analog aligned with the analog development itself. Hierarchy doesn’t always match. Wires can only carry voltage or current but not both, further complicating things. AMS assertions don’t work the same in all the different simulators.

Problem #4: When using CPF (for power policy) in the digital world it works well. But the checks with analog are not clean. There is no way to ensure that when a domain is powered down that an analog gate doesn’t float, for example. Or if the analog already contains a level shifter to make sure it doesn’t get doubled.

Problem #5: At 20/22nm and 14nm the problems are daunting. The process, tools and methodology are all developed concurrently. The number of design rules explodes. Variability goes way up.

On the other hand there have been huge advances in the last 5 years. Back when I was at Cadence we kicked off a program called Superchip that was supposed to merge the analog and digital design environments and also move them onto OpenAccess. It rapidly became clear we were years away from being able to do that (despite sales having committed it to a huge customer who had better remain nameless). But a lot of that vision is now a reality.

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