Here, I am talking about reliability of chip design in the context of electrical effects, not external factors like cosmic rays. So, the electrical factors that could affect reliability of chips could be excessive power dissipation, noise, EM (Electromigration), ESD (Electrostatic Discharge), substrate noise coupling and the like. Any of these can become prominent in a chip due to mishandling of certain design aspects. And they can become critical for different types of chips leading to their failure. Appropriate care must be taken to detect them as early as possible in the design cycle and prevent.
This week, I attended a free webinarof ANSYS-Apache, presented by Vikram Shamirpeta. Vikram talked in great detail about these effects, their solutions and how Apache tools can be used to prevent them throughout the RTL to GDS stages. It was interesting to know about different types of analysis applied to different types of ASICs and SoCs; those were exemplified through case studies. As we know, now a days, analog-digital mixed signal and several IPs integrated together are part of almost all SoCs; I found specific interest in power management to accommodate all of these and managing noise introduced by digital circuitry into analog. Of course there are other important issues also to be taken care of. I am just going to summarise those here, but it’s worth attending the webinar to know the actual details. It’s just about 30 minutes, but the gains are considerable.
[RTL Power Optimization with an example to shut down clock when not required]
The above picture shows, how power saving can be done at the RTL level by setting the clock to be active only when required; such types of methods are meticulously utilized by the RTL Power Optimization tool, PowerArtist which is physical aware.
[Identifying connectivity failures, e.g. high resistance due to missing stacked via]
Totem can perform extensive checks on the layout to find any violation which can cause connectivity issues leading to electrical abnormalities.
[Power Integrity check, e.g. detecting worst instance not getting enough power]
Integrity of Power Delivery Network (PDN) has become important due to shrinking noise margin (as threshold voltage has remained constant, but supply voltage has decreased) and high performance requirement. In the above case, due to simultaneous switching of neighbouring instances, drawing maximum current through the same power grid, there is high voltage drop and hence the corresponding PDN needs adjustments.
[EM Analysis, e.g. detection of uneven current in a power line and its fix]
EM analysis takes care of Average, RMS and Peak current for both power and signal lines. Apache tools take into account all aspects of EM rules such as direction, temperature, topology, and VIA location.
[ESD Analysis with a case of failure due to ground connection during IP integration]
Excessive electrostatic discharge or electrical overstress (ESD) can cause device or interconnect failure. PathFinder can be used to find the root cause of ESD and fix.
[Substrate noise and its modelling to keep it under control]
As digital and analog circuitry sit on the same substrate, digital (aggressor) noise is injected into analog (victim) through the substrate coupling. A correct modelling of this noise injection must be done to keep it within limits. RedHawk and Totem use a smart extraction engine which can handle complex structures such as wide via arrays and metal structures.
Also, since a substantial portion of SoC is covered by various IPs, and they consume extensive power, their power integrity and reliability must be checked. Effect of various modes of operations of IPs at the top level must be validated. Totem can be used to analyze the layout down to transistor level.
Apache, in its Power Noise Reliability Platform has powerful tools such as PowerArtist for power analysis and fix at RTL level, RedHawk for system and full-chip level analysis and fix and Totem for AMS designs. These are high performance tools (with multi-threaded and multi-core architecture) which can handle large size flat designs of 100M+ transistors.
The webinar “Power Noise Reliability Sign-off of Custom Analog IPs” is worth going through; it provides good learning about today’s SoC issues and their solution.