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Accelerating SoC Simulation Times

Accelerating SoC Simulation Times
by Daniel Payne on 08-15-2013 at 2:43 pm

There never seems to be enough time in a SoC project to simulate all of the cycles and tests that you want to run, so any technique to accelerate each run is welcomed. You can just wait for your software-based RTL simulator to finish running, or you can consider using a hardware-based accelerator approach. I learned more about one such acceleration approach from Aldec at a recent webinar entitled, Accelerate SoC Simulation Time of Newer Generation FPGAs.


Bill Tomas, Aldec


Functional Verification Challenges

Bill started out by listing why functional verification has become a major bottleneck in the SoC design process:

  • FPGA-based SoC
  • Embedded Processors
  • IP Cores
  • Media interfaces
  • High-speed communication
  • Low-power methodologies
  • RTL, Gate and post-route simulations are limited by SW-based simulation speeds (good debugging with simulator)
  • Simulation runs for hours to weeks
  • SoC split into blocks, part of a larger team effort
  • Design partitioning across multiple FPGAs

HW Emulation

Emulators have been around for decades, and originally they were priced quite high, sometimes in the millions of dollars. Today with FPGA-based emulators the prices have come down dramatically, and Aldec has a system called Hardware Emulation Solutions (HES). Their approach uses the same board for both prototyping and simulation acceleration.

For verification interfaces it has SCE-MI emulation (Standard Co-Emulation Modeling Interface), which uses the Accellera standard, so it’s not proprietary.

Design Verification Manager (DVM) – setup emulation environment, FPGA source to bit files.

Static probes are selected before the logic synthesis step.

Emulators are slower than real time operation, so adding a speed adapter gives you In Circuit Emulation (ICE).

ASIC Prototyping Board

The HES-7 board uses the Virtex-7 FPGA for up to a 24M ASIC gate capacity, connecting up to 4 boards for a 96M gate capacity.

The backplane is open, well documented, and can be connected to your own hardware as needed. There’s a daughter board which includes the new Xilinx Zinc chip with ARM processor on-board.

Simulation Acceleration
To get simulation acceleration they use an HDL simulator connected to an FPGA board, where the testbench stays in the HDL simulator while the synthesized logic runs on the FPGA hardware. Your acceleration speed up depends on the size and activity of your testbench versus the DUT.

If your testbench used up 5% of the HDL simulator time, then acceleration would provide up to a 20X speed up. On the other end, if your testbench took up 50% of the HDL simulator time then the maximum acceleration would be only 2x.

Improving Simulation Speed

There were three ways to improve your simulation speeds:

  • Partitioning – automatic or manual, where manual would give you greater control.
  • HW memory mapping – use the RAMs in the FPGA
  • Replace your TB with a SystemC application

Advanced Debugging

HDL simulators provide 100% visibility into all nets of a design, making debug easier. Emulators have historically been limited in their visibility of nets. With Aldec’s system you have three choices for net visibility:

  • Static probes – pre-synthesis list of nodes to debug and view.
  • Dynamic probes – Uses the Xilinx read back feature to view registers while running.
  • Memory Visibility – in the HW debugger you can see the external memories and watch content changes, initialize RAM, etc.

Another thing that you want in debug is to compare nets in hardware versus the HDL simulator, to see if there are any differences.

Demo

Bill ran through a mostly live demo showing how all of the pieces fit and played together. In one small test case it simulated for 1709 seconds using just an HDL simulator, then with hardware emulation it accelerated to 900 seconds.

Summary

10X to 100X faster simulation times are now possible using hardware-based acceleration with Aldec’s HES system compared to sw-based simulation, and the exact speedup depends on your TB/DUT split.

Q&A

Q: My design has multiple clock domains, how does that work with emulation?
A: DVM does an auto transform of your clock domains, post synthesis. DVM uses multiple partitions.

Q: Static vs Dynamic probes?
A: Static – you setup and instrument pre-synthesis. The more probes the more instrumentation required.

Q: If I choose lots of signals or triggers, does it affect performance?
A: For triggers there is minimal impact. Yes, for more signals it will affect performance. Debug vs simulation speed trade-off.

Q: What is typical speed up with acceleration?
A: For emulation you’re running at MHz levels. The major bottleneck is between the HW/SW interface. If you use SCE-MI, that will eliminate the bottleneck.

Q: Can I use a Xilinx board with your emulation approach?
A: Our Aldec HES 7 boards are tuned for our emulation approach, so it doesn’t work with just any generic board.

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