Image RemovedIn 2016 we published our book “Prototypical: The Emergence of FPGA-Based Prototyping for SoC Design” which began an incredible journey through ASIC prototyping. While we are working on an update to that book there is some recent Prototyping news that is worthy of praise.
First and foremost, S2C Inc. has just announced… Read More
If you are considering an FPGA prototype for an ASIC or SoC as part of your verification strategy, which more and more chip designers today are doing to enhance verification coverage of complex designs, please take advantage of this webinar replay:
How ASIC/SoC Prototyping Solutions Can Help You!
Or to get a quick quote from S2C … Read More
In the semiconductor world when we hear “full-stack” we think of a chip, chipset or board with a bunch of software, which can be connected to sensors of various types on one end, trained networks in the middle and actuators on the other side. But of course that’s not really a full-stack. The real thing would be deployment of an entire… Read More
Recently, Daniel Nenni blogged on the presentation Wally Rhines gave at #56th DAC. Daniel provided a great summary, but I want to dive into a portion of the presentation in more detail. I love Wally’s presentations, but sometimes you cannot absorb the wealth of information he provides when you initially see it. It’s… Read More
FPGAs have been used for ASIC prototyping since the beginning of FPGAs (1980s) allowing hardware and software designers to work in harmony developing, testing, and optimizing their products. We covered the history of FPGAs in Chapter 3 of our book “Fabless: The Transformation of the Semiconductor Industry”, which includes … Read More
When I think of an IP development kit, I imagine software plus a hardware model I can run on a prototyper or, closer to the kits offered by semi companies, software plus a board hosting an FPGA implementation of the IP along with DDR memory, flash and a variety of interfaces. These approaches work well for IP providers because hardware… Read More
Periodically Mentor does us all a big favor by commissioning a survey of verification engineers across the world to illuminate trends in verification. This is valuable not only to satisfy our intellectual curiosity but also to help convince managers and finance mandarins that our enthusiasm to invest in new methods and tools … Read More
Hardware-assisted verification has been with us (commercially) for around 20 years and at this point is clearly mainstream. But during this evolution it split into at least two forms (emulation and prototyping), robbing us of a simple choice – to hardware-assist or not to hardware-assist (that is the question). Which in turn … Read More
FPGA-based prototyping has provided a major advance in verification and validation for complex hardware/software systems but even its most fervent proponents would admit that setup is not exactly push-button. It’s not uncommon to hear of weeks to setup a prototype or of the prototype finally being ready after you tape-out. … Read More
Pop quiz – name an event at which an EDA vendor would be unlikely to exhibit. How about The Trading Show in Chicago, later this month? That’s trading as in markets, high-frequency trading, blockchain and all that other trading-centric financial technology. This is another market, like cloud, where performance is everything and… Read More
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Prototyping with Intel's New 80M Gate FPGA and S2C!
Analyzing PowerMOS Devices to Reduce Power Loss and Improve Reliability
REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation
REPLAY: Avoiding CDM (Charged Device Model) ESD Failures
REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!"
REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification
REPLAY: Fabless: The Transformation of the Semiconductor Industry
REPLAY: The Brave New World of Customized Memory
REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning
REPLAY: VLSI Design Methodology Development
REPLAY: Lightspeed Data Sync - Design Workspace Problems Solved!
REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats?
REPLAY: How ASIC/SoC Prototyping Solutions Can Help You!
REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®
REPLAY: Taiwan ESD Workshop Recording
REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction
REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version)
REPLAY: Finding Your Way Through Verification
REPLAY: Concerned about IP security threats for your SoCs?
REPLAY: Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip
REPLAY: PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior
REPLAY: Thermal-induced Reliability Challenges and Solutions for Advanced IC Design
REPLAY: Choose the Right ASIC Manufacturing Model for Your Business
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Analyzing PowerMOS Devices to Reduce Power Loss and Improve Reliability
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REPLAY: Avoiding CDM (Charged Device Model) ESD Failures
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REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats?
REPLAY: How ASIC/SoC Prototyping Solutions Can Help You!
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REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction
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REPLAY: Concerned about IP security threats for your SoCs?
REPLAY: Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip
REPLAY: PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior
REPLAY: Thermal-induced Reliability Challenges and Solutions for Advanced IC Design
REPLAY: Choose the Right ASIC Manufacturing Model for Your Business
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Analyzing PowerMOS Devices to Reduce Power Loss and Improve Reliability
REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation
REPLAY: Avoiding CDM (Charged Device Model) ESD Failures
REPLAY: eFPGA – “What a great idea! But I have no idea how I’d use it!”
REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification
REPLAY: Fabless: The Transformation of the Semiconductor Industry
REPLAY: The Brave New World of Customized Memory
REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning
REPLAY: VLSI Design Methodology Development
REPLAY: Lightspeed Data Sync – Design Workspace Problems Solved!
REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats?
REPLAY: How ASIC/SoC Prototyping Solutions Can Help You!
REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®
REPLAY: Taiwan ESD Workshop Recording
REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction
REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version)
REPLAY: Finding Your Way Through Verification
REPLAY: Concerned about IP security threats for your SoCs?
REPLAY: Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip
REPLAY: PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior
REPLAY: Thermal-induced Reliability Challenges and Solutions for Advanced IC Design
REPLAY: Choose the Right ASIC Manufacturing Model for Your Business
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Why is Intel still short on chips?