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Corigine Logo SemiWiki
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Bringing Prototyping to the Desktop

Bringing Prototyping to the Desktop
by Kalar Rajendiran on 05-16-2022 at 6:00 am

A few months ago, I wrote about Corigine and their MimicPro FPGA prototyping system and MimicTurbo GT card solutions. That article went into the various features and benefits of the two solutions, with the requirements for next-generation prototyping solutions as the backdrop. You can access that article here. At 250+ employees, spread over 10+ sites around the world, the startup is well-established. It is on a mission to make prototyping solutions accessible to a wider audience of engineers, right on their desktop. Customers have also been providing feedback to Corigine based on their hands-on experience since the launch of these solutions last year.

I followed up with Corigine to identify some key differentiating aspects of their solutions against the traditional competitive solutions. This post is based on my conversation with Mike Shei, Head of R&D and Ali Khan, VP Business & Product Development.

Competitive Comparison

Corigine has incorporated lot of run time capabilities to their prototyping solutions compared to traditional prototyping solutions such as Synopsys HAPS. For example, the “Local Debug and System Scope” functionality provides high visibility to data right on the desktop, for quickly identifying and resolving bugs. The memory analyzer capability provides backdoor runtime memory access to both user design memories and external DDR memories. HAPS does not offer these kinds of capabilities.

Corigine’s solutions use the ASIC’s clock scheme compared to Cadence’s Protium which uses cycle-based fast clock scheme when running the design. As the real user clock will always be half of the fast clock, the performance will be degraded 50% from a system performance point of view. Protium also relies on the Palladium platform for the debug capability. Mimic does not rely on any emulator for performing the debug.

Corigine’s auto-partitioning tool takes a system level point of view to minimize the hops when routing between FPGAs in a multi-FPGA based design. Partitioning tools of competitive solutions consider the logical partitioning, physical partitioning and system routing as three independent steps. Whereas Corigine considers these three aspects in an integrated fashion, thereby yielding better system performance.

Customer Feedback

Software Development

Competitive prototyping and emulation systems are expensive and thus access by engineers is prioritized. Corigine is hearing from the customer base that their software engineers are competing with hardware verification engineers for access to these resources. That puts a crimp on the bigger goal of hardware/software co-development and co-verification. Hardware/software co-verification is a very important aspect of product development, for integration of software (sw) with hardware (hw) well before final chips and boards become available. A good prototyping system should allow for not only ease of verification of the hardware but also enable hardware validation, software development, debugging and hw/sw integration.

With Corigine’s MimicTurbo GT card solution, software engineers now have access right on their desktop irrespective of wherever in the world they may be based. They could now do their software co-development right from their desktop without having to wait for access to expensive emulation platforms.

Customers also want their software developers to have access in a distributed environment and the MimicTurbo GT card solution makes that possible.

Corigine MimicTurbo GT Card

Scalability

While each MimicTurbo GT card can handle a design up to 48 million gates, multiple cards can be used to handle larger designs. Corigine uses QSFP cables to interconnect multiple servers to deliver this expanded capability. Customers are able to tap just the right amount of hardware resources as called for.

Time to Market

There are many scenarios where customers have multiple versions of cores that need to be verified. For instance, multiple customized versions of RISC-V cores. These multiple verification runs can be done simultaneously on a number of desktops with MimicTurbo GT cards, thereby cutting down on time.

Opportunity For IP Vendors

IP vendors could verify their IP cores using the MimicTurbo GT card solution and then provide the card and the IP cores to their customers for quick verification by them. This should be attractive to customers as it would save them time and effort from having to set up a new verification system.

Also read:

A Next-Generation Prototyping System for ASIC and Pre-Silicon Software Development

Scaling is Failing with Moore’s Law and Dennard

High-speed, low-power, Hybrid ADC at IP-SoC

Why Software Rules AI Success at the Edge

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