Bringing Prototyping to the Desktop

Bringing Prototyping to the Desktop
by Kalar Rajendiran on 05-16-2022 at 6:00 am

Corigine MimicTurbo GT Card

A few months ago, I wrote about Corigine and their MimicPro FPGA prototyping system and MimicTurbo GT card solutions. That article went into the various features and benefits of the two solutions, with the requirements for next-generation prototyping solutions as the backdrop. You can access that article here. At 250+ employees,… Read More


CadenceTECHTALK: Using Protium Black-Box Flow to Implement Native Interfaces

CadenceTECHTALK: Using Protium Black-Box Flow to Implement Native Interfaces
by Admin on 12-16-2021 at 12:00 am

Using Protium Black-Box Flow to Implement Native Interfaces

December 16, 2021

Overview

Protium prototyping platform provides by far the fastest and easiest bring-up (time to prototype) of any prototype system in the market, combined with vastly higher runtime performance than emaulation system. But what if…

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Cadence Dynamic Duo Upgrade Debuts

Cadence Dynamic Duo Upgrade Debuts
by Bernard Murphy on 04-08-2021 at 6:00 am

Dynamic Duo min

Cadence calls their hardware acceleration platforms, Palladium Z2 for fast pre-silicon hardware debug and Protium X2 for fast pre-silicon software validation, their Dynamic Duo. With good reason. Hardware acceleration is now fundamental to managing the complexity of verification and validation for large systems, hardware… Read More


Blurring Boundaries

Blurring Boundaries
by Bernard Murphy on 12-05-2017 at 7:00 am

I think most of us have come to terms with the need for multiple verification platforms, from virtual prototyping, through static and formal verification, to simulation, emulation and FPGA-based prototyping. The verification problem space is simply too big, in size certainly but also in dynamic range, to be effectively addressed… Read More


Anirudh on Verification

Anirudh on Verification
by Bernard Murphy on 03-13-2017 at 7:00 am

I was fortunate to have a 1-on-1 with Anirudh before he delivered the keynote at DVCon. In case you don’t know the name, Dr. Anirudh Devgan is Executive VP and GM of the Digital & Signoff Group and the System & Verification Group at Cadence. He’s on a meteoric rise in the company, not least for what he has done for Cadence’s position… Read More


Prototyping: Sooner, Easier, Congruent

Prototyping: Sooner, Easier, Congruent
by Bernard Murphy on 02-28-2017 at 7:00 am

DVCon 2017 is a big week for Cadence verification announcements. They just released their Xcelium simulation acceleration product (on which I have another blog) and they have also released their latest and greatest prototyping solution in the Protium S1. This is new hardware based on Virtex UltraScale FPGAs on Cadence-designed… Read More


Aspirational Congruence

Aspirational Congruence
by Bernard Murphy on 02-07-2017 at 7:00 am

When talking to suppliers about their products, conversation tends to focus heavily on what they already have and why it is the answer to every imaginable need in their space. So it’s refreshing when a vendor wants to talk about where customers want to go without claiming they already have the answer wrapped up in a bow. I recently … Read More


Protium for the win in software development

Protium for the win in software development
by Don Dingee on 11-02-2016 at 4:00 pm

Cadence Design Systems is a long-standing provider in hardware emulation, but a relative newcomer to FPGA-based prototyping. In an upcoming lunch and learn session on November 11 in San Jose, Cadence teams will be outlining their productivity strategy. What’s different with their approach and why is this worth a lunch?… Read More


Software-Driven Verification Drives Tight Links between Emulation and Prototyping

Software-Driven Verification Drives Tight Links between Emulation and Prototyping
by Bernard Murphy on 04-28-2016 at 12:00 pm

I’ve mentioned many times what has become a very common theme in SoC and system verification – it has to be driven by the software because any concept of exhaustively verifying “everything” is neither feasible nor meaningful. Emulation has become a critical component of this flow in validating and regressing… Read More


A Brief History of FPGA Prototyping

A Brief History of FPGA Prototyping
by Paul McLellan on 09-25-2015 at 7:00 am

Verifying chip designs has always suffered from a two-pronged problem. The first problem is that actually building silicon is too expensive and too slow to use as a verification tool (when it happens, it is not a good thing and is called a “re-spin”). The second problem is that simulation is, and has always been, too slow.

When Xilinx… Read More