Cadence Design Systems is a long-standing provider in hardware emulation, but a relative newcomer to FPGA-based prototyping. In an upcoming lunch and learn session on November 11 in San Jose, Cadence teams will be outlining their productivity strategy. What’s different with their approach and why is this worth a lunch?
As we outlined in our book “Prototypical” in Chapter 3, Cadence officially broke into the FPGA-based prototyping space in May 2011 announcing a Rapid Prototyping Platform based on Altera FPGAs. With their second-generation Protium rapid prototyping platform introduced in July 2014, they moved to a Xilinx-based offering comparable to other solutions on the market.
A distinguishing feature of Protium is its software and set-up, designed so the bring-up flow is largely the same whether working with Protium or the Palladium hardware emulation environment. That is a huge plus for software teams that may have been grappling with the problem of communal access to the hardware emulator. It’s hard to get a lot of work done when one has to schedule short time slots on a shared piece of relatively expensive equipment.
Hardware emulation also has one significant drawback: co-verification with the real operating system in place is painfully slow, and maybe even practically impossible for a big OS plus application code. Emulation environments usually settle for running some verification test bench, with actual application code proven out somewhere else. Bottom line: while software types may be able to get some use out of the platforms, hardware emulators are really made for hardware types.
A better strategy has the hardware types still using the big hardware emulator for what it is good at, relatively easy setup and rapid iterations of hardware IP. Software types get more cost effective FPGA-based prototyping platforms to do what they are good at, being able to run actual code much more quickly on the actual hardware RTL implemented in FPGAs. Depending on the task at hand, perhaps some software types get their own platform to check out a specific IP block, while some get another dedicated platform for integration work.
Since the FPGA-based prototyping platforms are generally less expensive than hardware emulators, software teams can be outfitted with their own boxes. Once the FPGA-based prototyping platforms are set up, the software teams aren’t getting kicked off their machine constantly and can do more thorough exploration of the IP blocks.
People talk about productivity gains in prototyping, but the value of exploration may be even larger. When it comes to designing things like IoT SoCs that are in many ways -critical, deeply explored software may be all that stands between a device that is completely trusted and a device perceived as flaky or unusable. (Look up my presentation from earlier this year on “The Internet of Trust”.)
Now, back to the upcoming Protium lunch and learn. If your house is already using or considering Cadence Palladium emulator platforms, Protium FPGA-based platforms make a huge amount of sense. Hardware and software teams can work together without having to learn an all-new environment, and can share verification and debug strategies.
An important part of this lunch and learn is a look at how a Tensilica Vision DSP is set up on a Protium platform. Since the event is on the Cadence campus, there will be plenty of experts around. Also, there’s a little incentive besides the food: Cadence is giving away a Special Edition BB-8 Sphero with Force Band and a Ring Wi-Fi Smart Video Doorbell to one HW + SW team in attendance.
There’s a splash page for the event that leads to a registration form:
The big win for FPGA-based prototyping is to speed up embedded software development, both with a platform that is much faster than hardware emulation or simulation, and enabling more software developers on several prototyping systems simultaneously. I can’t join you there, but I’d enjoy hearing thoughts from anyone attending this event.Share this post via: