DVCon 2017 is a big week for Cadence verification announcements. They just released their Xcelium simulation acceleration product (on which I have another blog) and they have also released their latest and greatest prototyping solution in the Protium S1. This is new hardware based on Virtex UltraScale FPGAs on Cadence-designed boards, offering 6x higher capacity and an average 2x increase in performance. You can go from a single board at 25MG to a box at 200MG, and chain these together to get to 600MG. All that is important, but in one sense it’s not the most important aspect of this release. What’s really significant is getting to that power sooner, easier and with more confidence.
I talked about this in an earlier blog on Aspirational Congruence, based on a discussion with Frank Schirrmeister (Sr. Dir of Marketing at Cadence) on the importance of pipelining software development with hardware development and the importance to that goal of closely coupling emulation and prototyping. The fast version of that discussion is this. Embedded software development needs to start much earlier than late design implementation, yet some development and validation needs more accurate modeling than is available in virtual prototypes. FPGA-based prototyping is the best way to get there, but lengthy (months) and complex prototype setup has discouraged starting before the design is locked down, because there’s no time to do over if the design changes. This doesn’t help accelerate software development.
The way to cut this Gordian knot is to make prototype setup as fast and as hands-free as possible, while also closely tracking design verification models so you know that that behavior software developers will see on the prototype will be mirrored exactly in the behavior design verification engineers saw when that snapshot was taken. Frank gave me a prelude a few weeks ago to this concept of congruence between emulation and prototyping, meaning closely linked build, behavior and ease of transition between the two. Of course, this was a setup. He told me last week that Cadence are rolling out the solution this week at DVCon. Part of the solution is the Protium S1 but an equally important part is its close linkage with Palladium Z1 emulation.
Let’s start with compile. The platforms share a common compiler to the point that what you build for the emulator is guaranteed to behave the same way on the prototyper. Which means that you can check behavior in faster-setup emulation before committing to a prototype build, and you can be confident there won’t be surprise mismatches between the two. Even the post-partitioning model can be taken to the emulator for further debug and validation.
Then there’s place and route in each FPGA. Timing closure in FPGAs can be tricky which is one reason the S1 flow creates clocks locally in each FPGA. The flow automatically generates P&R constraints and guarantees hands-free closure across the design. Of course, you can still break into this flow to hand-tune for even higher performance. But based on stats they have published, out-of-the-box-performance is already pretty decent. And note that’s for a ~10x or more decrease in setup time.
Accessories such as speed-bridges can be reused between emulation and prototyping, another factor in congruence; your ICE modeling in emulation carries directly over to prototyping. Similarly transaction interfaces can be reused.
Cadence have also put a lot of work into the debug interface. For hardware, you can view waveforms across the design do force/release signal setting and set monitor probes, but of course the big focus in debug (given the target users) is for software. The S1 release includes a number of advances which should attract software developers and validators. Through a JTAG connection teams can download and upload/overwrite memory, control clocks, start and stop the design and they can write scripts around debug and test, all the features software developers expect in a full-featured debug environment. And naturally they can access the prototype remotely.
Cadence have a fulsome endorsement from the Xilinx integration and validation team who have validated the value early in product development, and apparently they have other early users in networking, consumer and storage applications.