Debugging an IC design at the transistor, Gate and RTL levels is often necessary to meet timing requirements and understand analog or digital behavior, yet the process itself can be a tedious one, filled with manual steps, therefore making it an error-prone process. EDA tools have been created to help us graphically debug transistor, Gate and RTL designs, and one company called Concept Engineeringis appearing at DACagain this year in Austin to showcase many incremental improvements to their debugging tools. To get an overview of Concept Engineering visit the Wiki page.
I first started using SpiceVision PRO more than a decade ago to read in a SPICE netlist, and then traverse it graphically by creating on-the-fly schematics when no schematics were available to me. This graphical view allowed me to quickly understand my SPICE netlist and its simulation behavior.
At DAC next week you’ll get an update on several improvements:
Many extraction tools create the SPEF format, so now you can use that input format for post-layout created netlists.
In the schematic viewer tool above you can see in the top window a very readable auto-generated schematic of an IC netlist, then by just clicking the interconnect between cells you see the RC interconnect appear in the lower window. This is a great time saver from having to stare at a text netlist to understand how the interconnect was extracted.
- Improved waveform viewing
- Improved automatic path extraction (points A to B)
- Improved clock tree visualization and clock domain crossing visualization.
Clock Tree Extraction
- Improved support for system-level visualization
- New support for stacked or arrayed components
- New logic cloud component that can include or hide logic elements and is represented by a cloud symbol
To see these improvements at DAC visit Concept Engineering in booth #1842, and ask for Gerhard Angst.
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