J38701 CadenceTECHTALK Automotive Design Banner 800x100 (1)
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4045
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4045
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
)

RTL Signoff Theater

RTL Signoff Theater
by Paul McLellan on 05-29-2013 at 11:00 am

 We have talked for years about RTL signoff, the idea that a design could be finalized at the RTL level and then most of the signoff would take place there. Then the design would be passed to a physical implementation team who would not expect to run into any problems (such as routing congestion, missing the power budget or similar problems). Obviously this requires tools that run at the RTL level that have adequate predictive power to spot problems so they can be resolved prior to handoff. In particular, since so many designs are essentially assembly of pre-designed IP, they need to work on blocks of IP and pick up potential problems. Further, to be useful, tools for doing this need to run fast otherwise there is no big gain versus doing a trial layout with the full synthesis, place & route suite. The trick is to get almost as much accuracy as you would from doing the full design at a fraction of the cost in runtime and, indirectly, tool license costs.

Atrenta’s Spyglass, in its various flavors, does just this. It works at the RTL level to provide good accuracy and fast runtimes to ensure that the RTL is “good”.

During DAC, Atrenta is running a series of customer/partner presentations in their RTL Signoff Theater. SO stands for Signoff.

[TABLE] class=”cms_table_grid” style=”width: 480px”
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” style=”text-align: center” | Time

| class=”cms_table_grid_td” style=”text-align: center” | Monday
| class=”cms_table_grid_td” style=”text-align: center” | Tuesday
| class=”cms_table_grid_td” style=”text-align: center” | Wednesday
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | 9.30
| class=”cms_table_grid_td” |
| class=”cms_table_grid_td” | Juniper: Power SO
| class=”cms_table_grid_td” | Juniper: Power SO
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | 10.30
| class=”cms_table_grid_td” | IPextreme: IP SO
| class=”cms_table_grid_td” | CEA-Leti: Power SO
| class=”cms_table_grid_td” | Cisco: CDC SO
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | 11.30
| class=”cms_table_grid_td” | CEA-Leti: Power SO
| class=”cms_table_grid_td” | Mentor: Power SO
| class=”cms_table_grid_td” | IPextreme: IP SO
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | 12.30
| class=”cms_table_grid_td” | Atrenta: What is RTL SO?
| class=”cms_table_grid_td” | TSMC: IP SO
| class=”cms_table_grid_td” | CEA-Leti: Power SO
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | 1.30
| class=”cms_table_grid_td” |
| class=”cms_table_grid_td” |
| class=”cms_table_grid_td” | TSMC: IP Signoff
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | 2.30
| class=”cms_table_grid_td” | TSMC: IP SO
| class=”cms_table_grid_td” | Cisco: CDC SO
| class=”cms_table_grid_td” |
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | 3.30
| class=”cms_table_grid_td” | Tensilica/CDN: IP Market
| class=”cms_table_grid_td” | Atrenta: What is RTL SO?
| class=”cms_table_grid_td” | Atrenta: What is RTL SO?
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | 4.30
| class=”cms_table_grid_td” | Juniper: Power SO
| class=”cms_table_grid_td” | IPextreme: IP SO
| class=”cms_table_grid_td” |
|-

Every day at 5.30 there will be a drawing for an iPad mini.

Full details of Atrenta activities at DAC, including links for registration, are here. Atrenta is at booth 1847.

Share this post via:

Comments

There are no comments yet.

You must register or log in to view/post comments.