12 Reasons to Attend this Annual User Group Meeting for Transistor-level IC Designers

12 Reasons to Attend this Annual User Group Meeting for Transistor-level IC Designers
by Daniel Payne on 10-07-2015 at 7:00 am

My first job out of college was transistor-level circuit design of DRAMs at Intel, so I’ve continued to be fascinated with both the craft and science of designing, optimizing, verifying and debugging custom ICs. Last October I traveled to Munich, Germany to attend a two day user group meeting for engineers using tools from… Read More


Transistor-Level IC Design is Alive and Thriving

Transistor-Level IC Design is Alive and Thriving
by Daniel Payne on 11-26-2014 at 7:00 am

There’s much talk in EDA about High Level Synthesis (HLS), Transaction Level Modeling (TLM) and the Universal Verification Methodology (UVM), however there’s a lower-level of abstraction, the transistor-level, where high-speed digital cell libraries are created, analog circuits are crafted, and AMS designers… Read More


Transistor, Gate and RTL Debug Update at DAC

Transistor, Gate and RTL Debug Update at DAC
by Daniel Payne on 05-29-2013 at 10:53 am

Debugging an IC design at the transistor, Gate and RTL levels is often necessary to meet timing requirements and understand analog or digital behavior, yet the process itself can be a tedious one, filled with manual steps, therefore making it an error-prone process. EDA tools have been created to help us graphically debug transistor,… Read More