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Transistor-Level IC Design is Alive and Thriving

Transistor-Level IC Design is Alive and Thriving
by Daniel Payne on 11-26-2014 at 7:00 am

There’s much talk in EDA about High Level Synthesis (HLS), Transaction Level Modeling (TLM) and the Universal Verification Methodology (UVM), however there’s a lower-level of abstraction, the transistor-level, where high-speed digital cell libraries are created, analog circuits are crafted, and AMS designers tweak transistor sizes and choose circuit topologies in order to meet stringent specifications. At the transistor level the IC designers have many challenges, like:

  • Will my circuit be robust and work across all PVT conditions?
  • How does process variation effect the yield of my design?
  • Is my design optimized?
  • How do I port from 90 nm to 65 nm?
  • Does this analog topology work with FinFET processes?

Related – Transistor-level Sizing Optimization

One EDA company founded in 2001 has a focus on tools used for interactive, manual, semi- and fully automatic analysis, sizing, design centering and yield optimization of analog and mixed-signal circuits. Their annual user group meetingwas last week in Munich, and I attended to learn first-hand. The company is called MunEDA, pronounced moo-nee-dah.


An Example MOS Op Amp Circuit

The user group meeting started on Monday when Pierluigi Daglio from STMicroelectronics gave an overview of previous years, dating back to 2006. I first met Pierluigi back in 2010 when he was on a panel that I moderated at DACon the topic – Hot and SPICEy: Users Review Different Flavors of SPICE and FastSPICE.


Pierluigi Daglio, STMicroelectronics

Related – An IO Design Optimization Flow for Reliability in 28 nm CMOS

Over the next two days we had 29 presentations, complete with Q&A to learn more about getting the best results out of transistor-level designs. Here’s a quick list of presentation titles:

  • ICScape – Accelerate Design Closure
  • MunEDA – Statistical Verification and Analysis Tools
  • SMIC – Process related yield debug and optimization of analog IP with MunEDA WiCKeD
  • Lantiq – Sign-off flow for RF design with WiCkeD in a 65nm Technology
  • Novatek – S&H Sample & Hold (ADC) Mismatch Analysis and Sizing using WiCkeD
  • IPGEN – New layout generation techniques for variation sensitive analog circuits
  • MunEDA – Reliability & Robustness Based Design Using WiCkeD
  • STMicroelectronics – I/O Design Optimization Flow for Reliability In Advanced CMOS Nodes
  • Infineon – Reliability Aware Design of Relaxation Oscillator in Advanced CMOS Technology Nodes with WiCkeD
  • STMicroelectronics – IOs circuit optimization activities to enhance productivity, circuit robustness and improve existing reliability flow
  • Sapienza University Rome– Digital standard cell noise margin optimization, also considering aging effects with MunEDA WiCkeD and
    Synopsys MOSRA tools (MANON)

  • Infineon – Safeguarding Hold time Margin for Internal Scan Chain in Multibit-Register Standard cells
  • Altera – Distributed Memory Design (MLAB) – design optimization and worst case analysis on memory cells, data paths and write pulse
    generators with WiCkeD

  • MunEDA – Advances in Circuit Migration
  • HLMC – 55nm to 40nm Bandgap porting with SPT & High gain Amp optimization with MunEDA WiCkeD
  • Fraunhofer – Silicon Proof of the Intelligent Analog IP Design Flow using WiCkeD
  • MunEDA – Full-Custom Low Power Design Methodology with MunEDA WiCkeD
  • MunEDA – Ultra High Sigma (6+ Sigma) Analysis – High Sigma is not enough
  • STMicroelectronics – Corner Verification and Design Optimization in Smart Power & Non-Volatile Memory Technologies
  • University Frankfurt – FEATS – explorative automated topology synthesis with WiCkeD
  • Fraunhofer – Advanced measures for OpAmp optimization with WiCkeD
  • STMicroelectronics – Design validation and development of RF macrocells
  • ARP Microsystems – High-Voltage Automotive Analog IP Development for SOC using WiCkeD tools
  • Altera – Full-custom and Semi-custom Clock Trees Optimization using MunEDA WiCkeD – Clock Skew Matching, Clock Insertion Delay
    and Duty-Cycle

  • STMicroelectronics – SMAC – Smart components and Smart Systems integration

Foundry partners included: STMicroelectronics, SMIC and HLMC. I had heard about the first two foundries, but HLMC located in Shanghai was new to me, and they offer 90 nm, 65 nm and 45 nm processes into markets like: standard CMOS, AMS, RF CMOS and NOR Flash.

Related – Debugging a 10 bit SAR ADS to Improve Yield

EDA partners were: ICScape, IPGen. We’ve blogged about ICScape on SemiWiki last year, and then IPGen is a small startup with IC layout generation technology plus services.


Reimund Wittman, CTO, IPGEN

Each of the presentations were made using PowerPoint, and then attendees had a hard-copy handout which will be followed up with an online version with video archives for registered users. We had plenty of time to network and socialize during coffee breaks, lunch and a fabulous dinner on Monday night at the Agustiner Brewery.


Agustiner Brewery

The most creative presentation had to be from the University Frankfurt, where they had an analog synthesis framework that included expert knowledge to produce a wide variety of circuit topologies. They connected their framework to the circuit sizing optimization in the MunEDA WiCkeD tool.


Markus Meissner, University Frankfurt

On the fast digital side was a paper from Altera about how they optimized the transistor sizes for clock trees used inside of their latest FPGA designs.


B.Y. Ng, Altera

Overall I learned that transistor-level IC design is alive and thriving, thanks to the University curriculum on AMS design techniques, commercial practice of circuit design, demand from foundries for libraries, and finally EDA tools that enable analysis and optimization.


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